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ATtiny2313

[tn2313def.inc] [iotn2313.h]

;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** ;***** Created: 2009-11-03 14:40 ******* Source: ATtiny2313.xml ********** ;************************************************************************* ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y ;* ;* Number : AVR000 ;* File Name : "tn2313def.inc" ;* Title : Register/Bit Definitions for the ATtiny2313 ;* Date : 2009-11-03 ;* Version : 2.35 ;* Support E-mail : avr@atmel.com ;* Target MCU : ATtiny2313 ;* ;* DESCRIPTION ;* When including this file in the assembly program file, all I/O register ;* names and I/O register bit names appearing in the data book can be used. ;* In addition, the six registers forming the three data pointers X, Y and ;* Z have been assigned names XL - ZH. Highest RAM address for Internal ;* SRAM is also defined ;* ;* The Register names are represented by their hexadecimal address. ;* ;* The Register Bit names are represented by their bit number (0-7). ;* ;* Please observe the difference in using the bit names with instructions ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" ;* (skip if bit in register set/cleared). The following example illustrates ;* this: ;* ;* in r16,PORTB ;read PORTB latch ;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) ;* out PORTB,r16 ;output to PORTB ;* ;* in r16,TIFR ;read the Timer Interrupt Flag Register ;* sbrc r16,TOV0 ;test the overflow flag (use bit#) ;* rjmp TOV0_is_set ;jump if set ;* ... ;otherwise do something else ;************************************************************************* #ifndef _TN2313DEF_INC_ #define _TN2313DEF_INC_ #pragma partinc 0 ; ***** SPECIFY DEVICE *************************************************** .device ATtiny2313 #pragma AVRPART ADMIN PART_NAME ATtiny2313 .equ SIGNATURE_000 = 0x1e .equ SIGNATURE_001 = 0x91 .equ SIGNATURE_002 = 0x0a #pragma AVRPART CORE CORE_VERSION V2 #pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z+ ; ***** I/O REGISTER DEFINITIONS ***************************************** ; NOTE: ; Definitions marked "MEMORY MAPPED"are extended I/O ports ; and cannot be used with IN/OUT instructions .equ SREG = 0x3f .equ SPL = 0x3d .equ OCR0B = 0x3c .equ GIMSK = 0x3b .equ EIFR = 0x3a .equ TIMSK = 0x39 .equ TIFR = 0x38 .equ SPMCSR = 0x37 .equ OCR0A = 0x36 .equ MCUCR = 0x35 .equ MCUSR = 0x34 .equ TCCR0B = 0x33 .equ TCNT0 = 0x32 .equ OSCCAL = 0x31 .equ TCCR0A = 0x30 .equ TCCR1A = 0x2f .equ TCCR1B = 0x2e .equ TCNT1L = 0x2c .equ TCNT1H = 0x2d .equ OCR1AL = 0x2a .equ OCR1AH = 0x2b .equ OCR1BL = 0x28 .equ OCR1BH = 0x29 .equ CLKPR = 0x26 .equ ICR1L = 0x24 .equ ICR1H = 0x25 .equ GTCCR = 0x23 .equ TCCR1C = 0x22 .equ WDTCR = 0x21 .equ PCMSK = 0x20 .equ EEAR = 0x1e .equ EEDR = 0x1d .equ EECR = 0x1c .equ PORTA = 0x1b .equ DDRA = 0x1a .equ PINA = 0x19 .equ PORTB = 0x18 .equ DDRB = 0x17 .equ PINB = 0x16 .equ GPIOR2 = 0x15 .equ GPIOR1 = 0x14 .equ GPIOR0 = 0x13 .equ PORTD = 0x12 .equ DDRD = 0x11 .equ PIND = 0x10 .equ USIDR = 0x0f .equ USISR = 0x0e .equ USICR = 0x0d .equ UDR = 0x0c .equ UCSRA = 0x0b .equ UCSRB = 0x0a .equ UBRRL = 0x09 .equ ACSR = 0x08 .equ UCSRC = 0x03 .equ UBRRH = 0x02 .equ DIDR = 0x01 ; ***** BIT DEFINITIONS ************************************************** ; ***** PORTB ************************ ; PORTB - Port B Data Register .equ PORTB0 = 0 ; Port B Data Register bit 0 .equ PB0 = 0 ; For compatibility .equ PORTB1 = 1 ; Port B Data Register bit 1 .equ PB1 = 1 ; For compatibility .equ PORTB2 = 2 ; Port B Data Register bit 2 .equ PB2 = 2 ; For compatibility .equ PORTB3 = 3 ; Port B Data Register bit 3 .equ PB3 = 3 ; For compatibility .equ PORTB4 = 4 ; Port B Data Register bit 4 .equ PB4 = 4 ; For compatibility .equ PORTB5 = 5 ; Port B Data Register bit 5 .equ PB5 = 5 ; For compatibility .equ PORTB6 = 6 ; Port B Data Register bit 6 .equ PB6 = 6 ; For compatibility .equ PORTB7 = 7 ; Port B Data Register bit 7 .equ PB7 = 7 ; For compatibility ; DDRB - Port B Data Direction Register .equ DDB0 = 0 ; Port B Data Direction Register bit 0 .equ DDB1 = 1 ; Port B Data Direction Register bit 1 .equ DDB2 = 2 ; Port B Data Direction Register bit 2 .equ DDB3 = 3 ; Port B Data Direction Register bit 3 .equ DDB4 = 4 ; Port B Data Direction Register bit 4 .equ DDB5 = 5 ; Port B Data Direction Register bit 5 .equ DDB6 = 6 ; Port B Data Direction Register bit 6 .equ DDB7 = 7 ; Port B Data Direction Register bit 7 ; PINB - Port B Input Pins .equ PINB0 = 0 ; Port B Input Pins bit 0 .equ PINB1 = 1 ; Port B Input Pins bit 1 .equ PINB2 = 2 ; Port B Input Pins bit 2 .equ PINB3 = 3 ; Port B Input Pins bit 3 .equ PINB4 = 4 ; Port B Input Pins bit 4 .equ PINB5 = 5 ; Port B Input Pins bit 5 .equ PINB6 = 6 ; Port B Input Pins bit 6 .equ PINB7 = 7 ; Port B Input Pins bit 7 ; ***** TIMER_COUNTER_0 ************** ; TIMSK - Timer/Counter Interrupt Mask Register .equ OCIE0A = 0 ; Timer/Counter0 Output Compare Match A Interrupt Enable .equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable .equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable ; TIFR - Timer/Counter Interrupt Flag register .equ OCF0A = 0 ; Timer/Counter0 Output Compare Flag 0A .equ TOV0 = 1 ; Timer/Counter0 Overflow Flag .equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B ; OCR0B - Timer/Counter0 Output Compare Register .equ OCR0_0 = 0 ; .equ OCR0_1 = 1 ; .equ OCR0_2 = 2 ; .equ OCR0_3 = 3 ; .equ OCR0_4 = 4 ; .equ OCR0_5 = 5 ; .equ OCR0_6 = 6 ; .equ OCR0_7 = 7 ; ; OCR0A - Timer/Counter0 Output Compare Register .equ OCR0A_0 = 0 ; .equ OCR0A_1 = 1 ; .equ OCR0A_2 = 2 ; .equ OCR0A_3 = 3 ; .equ OCR0A_4 = 4 ; .equ OCR0A_5 = 5 ; .equ OCR0A_6 = 6 ; .equ OCR0A_7 = 7 ; ; TCCR0A - Timer/Counter Control Register A .equ WGM00 = 0 ; Waveform Generation Mode .equ WGM01 = 1 ; Waveform Generation Mode .equ COM0B0 = 4 ; Compare Match Output B Mode .equ COM0B1 = 5 ; Compare Match Output B Mode .equ COM0A0 = 6 ; Compare Match Output A Mode .equ COM0A1 = 7 ; Compare Match Output A Mode ; TCNT0 - Timer/Counter0 .equ TCNT0_0 = 0 ; .equ TCNT0_1 = 1 ; .equ TCNT0_2 = 2 ; .equ TCNT0_3 = 3 ; .equ TCNT0_4 = 4 ; .equ TCNT0_5 = 5 ; .equ TCNT0_6 = 6 ; .equ TCNT0_7 = 7 ; ; TCCR0B - Timer/Counter Control Register B .equ TCCR0 = TCCR0B ; For compatibility .equ CS00 = 0 ; Clock Select .equ CS01 = 1 ; Clock Select .equ CS02 = 2 ; Clock Select .equ WGM02 = 3 ; .equ FOC0B = 6 ; Force Output Compare B .equ FOC0A = 7 ; Force Output Compare B ; ***** TIMER_COUNTER_1 ************** ; TIMSK - Timer/Counter Interrupt Mask Register .equ ICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable .equ TICIE = ICIE1 ; For compatibility .equ OCIE1B = 5 ; Timer/Counter1 Output CompareB Match Interrupt Enable .equ OCIE1A = 6 ; Timer/Counter1 Output CompareA Match Interrupt Enable .equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable ; TIFR - Timer/Counter Interrupt Flag register .equ ICF1 = 3 ; Input Capture Flag 1 .equ OCF1B = 5 ; Output Compare Flag 1B .equ OCF1A = 6 ; Output Compare Flag 1A .equ TOV1 = 7 ; Timer/Counter1 Overflow Flag ; TCCR1A - Timer/Counter1 Control Register A .equ WGM10 = 0 ; Pulse Width Modulator Select Bit 0 .equ PWM10 = WGM10 ; For compatibility .equ WGM11 = 1 ; Pulse Width Modulator Select Bit 1 .equ PWM11 = WGM11 ; For compatibility .equ COM1B0 = 4 ; Comparet Ouput Mode 1B, bit 0 .equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 .equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0 .equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 ; TCCR1B - Timer/Counter1 Control Register B .equ CS10 = 0 ; Clock Select bit 0 .equ CS11 = 1 ; Clock Select 1 bit 1 .equ CS12 = 2 ; Clock Select1 bit 2 .equ WGM12 = 3 ; Waveform Generation Mode Bit 2 .equ CTC1 = WGM12 ; For compatibility .equ WGM13 = 4 ; Waveform Generation Mode Bit 3 .equ ICES1 = 6 ; Input Capture 1 Edge Select .equ ICNC1 = 7 ; Input Capture 1 Noise Canceler ; TCCR1C - Timer/Counter1 Control Register C .equ FOC1B = 6 ; Force Output Compare for Channel B .equ FOC1A = 7 ; Force Output Compare for Channel A ; ***** WATCHDOG ********************* ; WDTCR - Watchdog Timer Control Register .equ WDTCSR = WDTCR ; For compatibility .equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 .equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 .equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 .equ WDE = 3 ; Watch Dog Enable .equ WDCE = 4 ; Watchdog Change Enable .equ WDTOE = WDCE ; For compatibility .equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3 .equ WDIE = 6 ; Watchdog Timeout Interrupt Enable .equ WDIF = 7 ; Watchdog Timeout Interrupt Flag ; ***** EXTERNAL_INTERRUPT *********** ; GIMSK - General Interrupt Mask Register .equ PCIE = 5 ; .equ INT0 = 6 ; External Interrupt Request 0 Enable .equ INT1 = 7 ; External Interrupt Request 1 Enable ; EIFR - Extended Interrupt Flag Register .equ GIFR = EIFR ; For compatibility .equ PCIF = 5 ; .equ INTF0 = 6 ; External Interrupt Flag 0 .equ INTF1 = 7 ; External Interrupt Flag 1 ; ***** USART ************************ ; UDR - USART I/O Data Register .equ UDR0 = 0 ; USART I/O Data Register bit 0 .equ UDR1 = 1 ; USART I/O Data Register bit 1 .equ UDR2 = 2 ; USART I/O Data Register bit 2 .equ UDR3 = 3 ; USART I/O Data Register bit 3 .equ UDR4 = 4 ; USART I/O Data Register bit 4 .equ UDR5 = 5 ; USART I/O Data Register bit 5 .equ UDR6 = 6 ; USART I/O Data Register bit 6 .equ UDR7 = 7 ; USART I/O Data Register bit 7 ; UCSRA - USART Control and Status Register A .equ USR = UCSRA ; For compatibility .equ MPCM = 0 ; Multi-processor Communication Mode .equ U2X = 1 ; Double the USART Transmission Speed .equ UPE = 2 ; USART Parity Error .equ PE = UPE ; For compatibility .equ DOR = 3 ; Data overRun .equ FE = 4 ; Framing Error .equ UDRE = 5 ; USART Data Register Empty .equ TXC = 6 ; USART Transmitt Complete .equ RXC = 7 ; USART Receive Complete ; UCSRB - USART Control and Status Register B .equ UCR = UCSRB ; For compatibility .equ TXB8 = 0 ; Transmit Data Bit 8 .equ RXB8 = 1 ; Receive Data Bit 8 .equ UCSZ2 = 2 ; Character Size .equ CHR9 = UCSZ2 ; For compatibility .equ TXEN = 3 ; Transmitter Enable .equ RXEN = 4 ; Receiver Enable .equ UDRIE = 5 ; USART Data register Empty Interrupt Enable .equ TXCIE = 6 ; TX Complete Interrupt Enable .equ RXCIE = 7 ; RX Complete Interrupt Enable ; UCSRC - USART Control and Status Register C .equ UCPOL = 0 ; Clock Polarity .equ UCSZ0 = 1 ; Character Size Bit 0 .equ UCSZ1 = 2 ; Character Size Bit 1 .equ USBS = 3 ; Stop Bit Select .equ UPM0 = 4 ; Parity Mode Bit 0 .equ UPM1 = 5 ; Parity Mode Bit 1 .equ UMSEL = 6 ; USART Mode Select .equ UBRR = UBRRL ; For compatibility ; ***** ANALOG_COMPARATOR ************ ; ACSR - Analog Comparator Control And Status Register .equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 .equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 .equ ACIC = 2 ; .equ ACIE = 3 ; Analog Comparator Interrupt Enable .equ ACI = 4 ; Analog Comparator Interrupt Flag .equ ACO = 5 ; Analog Compare Output .equ ACBG = 6 ; Analog Comparator Bandgap Select .equ ACD = 7 ; Analog Comparator Disable ; DIDR - Digital Input Disable Register 1 .equ AIN0D = 0 ; AIN0 Digital Input Disable .equ AIN1D = 1 ; AIN1 Digital Input Disable ; ***** PORTD ************************ ; PORTD - Data Register, Port D .equ PORTD0 = 0 ; .equ PD0 = 0 ; For compatibility .equ PORTD1 = 1 ; .equ PD1 = 1 ; For compatibility .equ PORTD2 = 2 ; .equ PD2 = 2 ; For compatibility .equ PORTD3 = 3 ; .equ PD3 = 3 ; For compatibility .equ PORTD4 = 4 ; .equ PD4 = 4 ; For compatibility .equ PORTD5 = 5 ; .equ PD5 = 5 ; For compatibility .equ PORTD6 = 6 ; .equ PD6 = 6 ; For compatibility ; DDRD - Data Direction Register, Port D .equ DDD0 = 0 ; .equ DDD1 = 1 ; .equ DDD2 = 2 ; .equ DDD3 = 3 ; .equ DDD4 = 4 ; .equ DDD5 = 5 ; .equ DDD6 = 6 ; ; PIND - Input Pins, Port D .equ PIND0 = 0 ; .equ PIND1 = 1 ; .equ PIND2 = 2 ; .equ PIND3 = 3 ; .equ PIND4 = 4 ; .equ PIND5 = 5 ; .equ PIND6 = 6 ; ; ***** EEPROM *********************** ; EEAR - EEPROM Read/Write Access .equ EEARL = EEAR ; For compatibility .equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0 .equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1 .equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2 .equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3 .equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4 .equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5 .equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6 ; EEDR - EEPROM Data Register .equ EEDR0 = 0 ; EEPROM Data Register bit 0 .equ EEDR1 = 1 ; EEPROM Data Register bit 1 .equ EEDR2 = 2 ; EEPROM Data Register bit 2 .equ EEDR3 = 3 ; EEPROM Data Register bit 3 .equ EEDR4 = 4 ; EEPROM Data Register bit 4 .equ EEDR5 = 5 ; EEPROM Data Register bit 5 .equ EEDR6 = 6 ; EEPROM Data Register bit 6 .equ EEDR7 = 7 ; EEPROM Data Register bit 7 ; EECR - EEPROM Control Register .equ EERE = 0 ; EEPROM Read Enable .equ EEPE = 1 ; EEPROM Write Enable .equ EEWE = EEPE ; For compatibility .equ EEMPE = 2 ; EEPROM Master Write Enable .equ EEMWE = EEMPE ; For compatibility .equ EERIE = 3 ; EEProm Ready Interrupt Enable .equ EEPM0 = 4 ; .equ EEPM1 = 5 ; ; ***** PORTA ************************ ; PORTA - Port A Data Register .equ PORTA0 = 0 ; Port A Data Register bit 0 .equ PA0 = 0 ; For compatibility .equ PORTA1 = 1 ; Port A Data Register bit 1 .equ PA1 = 1 ; For compatibility .equ PORTA2 = 2 ; Port A Data Register bit 2 .equ PA2 = 2 ; For compatibility ; DDRA - Port A Data Direction Register .equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 .equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 .equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 ; PINA - Port A Input Pins .equ PINA0 = 0 ; Input Pins, Port A bit 0 .equ PINA1 = 1 ; Input Pins, Port A bit 1 .equ PINA2 = 2 ; Input Pins, Port A bit 2 ; ***** CPU ************************** ; SREG - Status Register .equ SREG_C = 0 ; Carry Flag .equ SREG_Z = 1 ; Zero Flag .equ SREG_N = 2 ; Negative Flag .equ SREG_V = 3 ; Two's Complement Overflow Flag .equ SREG_S = 4 ; Sign Bit .equ SREG_H = 5 ; Half Carry Flag .equ SREG_T = 6 ; Bit Copy Storage .equ SREG_I = 7 ; Global Interrupt Enable ; SPMCSR - Store Program Memory Control and Status register .equ SPMEN = 0 ; Store Program Memory Enable .equ PGERS = 1 ; Page Erase .equ PGWRT = 2 ; Page Write .equ RFLB = 3 ; Read Fuse and Lock Bits .equ CTPB = 4 ; Clear Temporary Page Buffer ; MCUCR - MCU Control Register .equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 .equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 .equ ISC10 = 2 ; Interrupt Sense Control 1 bit 0 .equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1 .equ SM0 = 4 ; Sleep Mode Select Bit 0 .equ SM = SM0 ; For compatibility .equ SE = 5 ; Sleep Enable .equ SM1 = 6 ; Sleep Mode Select Bit 1 .equ PUD = 7 ; Pull-up Disable ; CLKPR - Clock Prescale Register .equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 .equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 .equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 .equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 .equ CLKPCE = 7 ; Clock Prescaler Change Enable ; MCUSR - MCU Status register .equ PORF = 0 ; Power-On Reset Flag .equ EXTRF = 1 ; External Reset Flag .equ BORF = 2 ; Brown-out Reset Flag .equ WDRF = 3 ; Watchdog Reset Flag ; OSCCAL - Oscillator Calibration Register .equ CAL0 = 0 ; Oscillatro Calibration Value Bit 0 .equ CAL1 = 1 ; Oscillatro Calibration Value Bit 1 .equ CAL2 = 2 ; Oscillatro Calibration Value Bit 2 .equ CAL3 = 3 ; Oscillatro Calibration Value Bit 3 .equ CAL4 = 4 ; Oscillatro Calibration Value Bit 4 .equ CAL5 = 5 ; Oscillatro Calibration Value Bit 5 .equ CAL6 = 6 ; Oscillatro Calibration Value Bit 6 ; GTCCR - General Timer Counter Control Register .equ SFIOR = GTCCR ; For compatibility .equ PSR10 = 0 ; ; PCMSK - Pin-Change Mask register .equ PCINT0 = 0 ; Pin-Change Interrupt 0 .equ PCINT1 = 1 ; Pin-Change Interrupt 1 .equ PCINT2 = 2 ; Pin-Change Interrupt 2 .equ PCINT3 = 3 ; Pin-Change Interrupt 3 .equ PCINT4 = 4 ; Pin-Change Interrupt 4 .equ PCINT5 = 5 ; Pin-Change Interrupt 5 .equ PCINT6 = 6 ; Pin-Change Interrupt 6 .equ PCINT7 = 7 ; Pin-Change Interrupt 7 ; GPIOR2 - General Purpose I/O Register 2 .equ GPIOR20 = 0 ; General Purpose I/O Register 2 bit 0 .equ GPIOR21 = 1 ; General Purpose I/O Register 2 bit 1 .equ GPIOR22 = 2 ; General Purpose I/O Register 2 bit 2 .equ GPIOR23 = 3 ; General Purpose I/O Register 2 bit 3 .equ GPIOR24 = 4 ; General Purpose I/O Register 2 bit 4 .equ GPIOR25 = 5 ; General Purpose I/O Register 2 bit 5 .equ GPIOR26 = 6 ; General Purpose I/O Register 2 bit 6 .equ GPIOR27 = 7 ; General Purpose I/O Register 2 bit 7 ; GPIOR1 - General Purpose I/O Register 1 .equ GPIOR10 = 0 ; General Purpose I/O Register 1 bit 0 .equ GPIOR11 = 1 ; General Purpose I/O Register 1 bit 1 .equ GPIOR12 = 2 ; General Purpose I/O Register 1 bit 2 .equ GPIOR13 = 3 ; General Purpose I/O Register 1 bit 3 .equ GPIOR14 = 4 ; General Purpose I/O Register 1 bit 4 .equ GPIOR15 = 5 ; General Purpose I/O Register 1 bit 5 .equ GPIOR16 = 6 ; General Purpose I/O Register 1 bit 6 .equ GPIOR17 = 7 ; General Purpose I/O Register 1 bit 7 ; GPIOR0 - General Purpose I/O Register 0 .equ GPIOR00 = 0 ; General Purpose I/O Register 0 bit 0 .equ GPIOR01 = 1 ; General Purpose I/O Register 0 bit 1 .equ GPIOR02 = 2 ; General Purpose I/O Register 0 bit 2 .equ GPIOR03 = 3 ; General Purpose I/O Register 0 bit 3 .equ GPIOR04 = 4 ; General Purpose I/O Register 0 bit 4 .equ GPIOR05 = 5 ; General Purpose I/O Register 0 bit 5 .equ GPIOR06 = 6 ; General Purpose I/O Register 0 bit 6 .equ GPIOR07 = 7 ; General Purpose I/O Register 0 bit 7 ; ***** USI ************************** ; USIDR - USI Data Register .equ USIDR0 = 0 ; USI Data Register bit 0 .equ USIDR1 = 1 ; USI Data Register bit 1 .equ USIDR2 = 2 ; USI Data Register bit 2 .equ USIDR3 = 3 ; USI Data Register bit 3 .equ USIDR4 = 4 ; USI Data Register bit 4 .equ USIDR5 = 5 ; USI Data Register bit 5 .equ USIDR6 = 6 ; USI Data Register bit 6 .equ USIDR7 = 7 ; USI Data Register bit 7 ; USISR - USI Status Register .equ USICNT0 = 0 ; USI Counter Value Bit 0 .equ USICNT1 = 1 ; USI Counter Value Bit 1 .equ USICNT2 = 2 ; USI Counter Value Bit 2 .equ USICNT3 = 3 ; USI Counter Value Bit 3 .equ USIDC = 4 ; Data Output Collision .equ USIPF = 5 ; Stop Condition Flag .equ USIOIF = 6 ; Counter Overflow Interrupt Flag .equ USISIF = 7 ; Start Condition Interrupt Flag ; USICR - USI Control Register .equ USITC = 0 ; Toggle Clock Port Pin .equ USICLK = 1 ; Clock Strobe .equ USICS0 = 2 ; USI Clock Source Select Bit 0 .equ USICS1 = 3 ; USI Clock Source Select Bit 1 .equ USIWM0 = 4 ; USI Wire Mode Bit 0 .equ USIWM1 = 5 ; USI Wire Mode Bit 1 .equ USIOIE = 6 ; Counter Overflow Interrupt Enable .equ USISIE = 7 ; Start Condition Interrupt Enable ; ***** LOCKSBITS ******************************************************** .equ LB1 = 0 ; Lockbit .equ LB2 = 1 ; Lockbit ; ***** FUSES ************************************************************ ; LOW fuse bits .equ CKSEL0 = 0 ; Select Clock Source .equ CKSEL1 = 1 ; Select Clock Source .equ CKSEL2 = 2 ; Select Clock Source .equ CKSEL3 = 3 ; Select Clock Source .equ SUT0 = 4 ; Select start-up time .equ SUT1 = 5 ; Select start-up time .equ CKOUT = 6 ; Clock output .equ CKDIV8 = 7 ; Divide clock by 8 ; HIGH fuse bits .equ BODLEVEL0 = 0 ; Brown-out Detector trigger level .equ BODLEVEL1 = 1 ; Brown-out Detector trigger level .equ BODLEVEL2 = 2 ; Brown-out Detector trigger level .equ EESAVE = 3 ; EEPROM memory is preserved through chip erase .equ WDTON = 4 ; Watchdog Timer Always On .equ SPIEN = 5 ; Enable Serial programming and Data Downloading .equ DWEN = 6 ; debugWIRE Enable .equ RSTDISBL = 7 ; External reset disable ; EXTENDED fuse bits .equ SELFPRGEN = 0 ; Self Programming Enable ; ***** CPU REGISTER DEFINITIONS ***************************************** .def XH = r27 .def XL = r26 .def YH = r29 .def YL = r28 .def ZH = r31 .def ZL = r30 ; ***** DATA MEMORY DECLARATIONS ***************************************** .equ FLASHEND = 0x03ff ; Note: Word address .equ IOEND = 0x003f .equ SRAM_START = 0x0060 .equ SRAM_SIZE = 128 .equ RAMEND = 0x00df .equ XRAMEND = 0x0000 .equ E2END = 0x007f .equ EEPROMEND = 0x007f .equ EEADRBITS = 7 #pragma AVRPART MEMORY PROG_FLASH 2048 #pragma AVRPART MEMORY EEPROM 128 #pragma AVRPART MEMORY INT_SRAM SIZE 128 #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 ; ***** BOOTLOADER DECLARATIONS ****************************************** .equ NRWW_START_ADDR = 0x0 .equ NRWW_STOP_ADDR = 0x3ff .equ RWW_START_ADDR = 0x0 .equ RWW_STOP_ADDR = 0x0 .equ PAGESIZE = 16 ; ***** INTERRUPT VECTORS ************************************************ .equ INT0addr = 0x0001 ; External Interrupt Request 0 .equ INT1addr = 0x0002 ; External Interrupt Request 1 .equ ICP1addr = 0x0003 ; Timer/Counter1 Capture Event .equ OC1Aaddr = 0x0004 ; Timer/Counter1 Compare Match A .equ OC1addr = 0x0004 ; For compatibility .equ OVF1addr = 0x0005 ; Timer/Counter1 Overflow .equ OVF0addr = 0x0006 ; Timer/Counter0 Overflow .equ URXCaddr = 0x0007 ; USART, Rx Complete .equ URXC0addr = 0x0007 ; For compatibility .equ UDREaddr = 0x0008 ; USART Data Register Empty .equ UDRE0addr = 0x0008 ; For compatibility .equ UTXCaddr = 0x0009 ; USART, Tx Complete .equ UTXC0addr = 0x0009 ; For compatibility .equ ACIaddr = 0x000a ; Analog Comparator .equ PCIaddr = 0x000b ; .equ OC1Baddr = 0x000c ; .equ OC0Aaddr = 0x000d ; .equ OC0Baddr = 0x000e ; .equ USI_STARTaddr = 0x000f ; USI Start Condition .equ USI_OVFaddr = 0x0010 ; USI Overflow .equ ERDYaddr = 0x0011 ; .equ WDTaddr = 0x0012 ; Watchdog Timer Overflow .equ INT_VECTORS_SIZE = 19 ; size in words #endif /* _TN2313DEF_INC_ */ ; ***** END OF FILE ****************************************************** /* Copyright (c) 2004, 2005, 2006 Bob Paddock All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn2313.h,v 1.14.2.8 2009/02/11 18:44:42 arcanum Exp $ */ /* iotn2313.h derived from io2313.h by Bob Paddock. The changes between the AT90S2313 and the ATtiny2313 are extensive. Atmel has renamed several registers, and bits. See Atmel application note AVR091, as well as the errata at the end of the current ATtiny2313 data sheet. Some of the names have changed more than once during the sampling period of the ATtiny2313. Where there is no conflict the new and old names are both supported. In the case of a new feature in a register, only the new name is used. This intentionally breaks old code, so that there are no silent bugs. The source code must be updated to the new name in this case. The hardware interrupt vector table has changed from that of the AT90S2313. ATtiny2313 programs in page mode rather than the byte mode of the AT90S2313. Beware of programming the ATtiny2313 as a AT90S2313 device, when programming the Flash. ATtiny2313 has Signature Bytes: 0x1E 0x91 0x0A. Changes and/or additions are noted by "ATtiny" in the comments below. */ /* avr/iotn2313.h - definitions for ATtiny2313 */ #ifndef _AVR_IOTN2313_H_ #define _AVR_IOTN2313_H_ 1 /* This file should only be included from <avr/io.h>, never directly. */ #ifndef _AVR_IO_H_ # error "Include <avr/io.h> instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn2313.h" #else # error "Attempt to include more than one <avr/ioXXX.h> file." #endif /* I/O registers */ /* * The Register Bit names are represented by their bit number (0-7). * Example: PORTB |= _BV(PORTB7); Set MSB of PORTB. */ /* 0x00 Reserved */ /* ATtiny Digital Input Disable Register DIDR */ #define DIDR _SFR_IO8(0x01) #define AIN1D 1 #define AIN0D 0 /* ATtiny USART Baud Rate Register High UBBRH[11:8] */ #define UBRRH _SFR_IO8(0x02) /* ATtiny USART Control and Status Register C UCSRC */ #define UCSRC _SFR_IO8(0x03) #define UMSEL 6 #define UPM1 5 #define UPM0 4 #define USBS 3 #define UCSZ1 2 #define UCSZ0 1 #define UCPOL 0 /* 0x04 -> 0x07 Reserved */ /* ATtiny Analog Comparator Control and Status Register ACSR */ #define ACSR _SFR_IO8(0x08) #define ACD 7 #define ACBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 /* USART Baud Rate Register Low UBBRL[7:0] */ #define UBRRL _SFR_IO8(0x09) /* ATtiny USART Control Register UCSRB */ #define UCSRB _SFR_IO8(0x0A) #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define UCSZ2 2 #define RXB8 1 #define TXB8 0 /* ATtiny USART Status Register UCSRA */ #define UCSRA _SFR_IO8(0x0B) #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 #define UPE 2 #define U2X 1 #define MPCM 0 /* USART I/O Data Register UBR or RXB[7:0], TXB[7:0] */ #define UDR _SFR_IO8(0x0C) #define RXB _SFR_IO8(0x0C) #define TXB _SFR_IO8(0x0C) /* ATtiny USI Control Register USICR */ #define USICR _SFR_IO8(0x0D) #define USISIE 7 #define USIOIE 6 #define USIWM1 5 #define USIWM0 4 #define USICS1 3 #define USICS0 2 #define USICLK 1 #define USITC 0 /* ATtiny USI Status Register USISR */ #define USISR _SFR_IO8(0x0E) #define USISIF 7 #define USIOIF 6 #define USIPF 5 #define USIDC 4 #define USICNT3 3 #define USICNT2 2 #define USICNT1 1 #define USICNT0 0 /* ATtiny USI Data Register USIDR[7:0] */ #define USIDR _SFR_IO8(0x0F) /* Input Pins, Port D PIND[6:0] */ #define PIND _SFR_IO8(0x10) #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* Data Direction Register, Port D DDRD[6:0] */ #define DDRD _SFR_IO8(0x11) #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* Data Register, Port D PORTD[6:0] */ #define PORTD _SFR_IO8(0x12) #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* ATtiny General Purpose I/O Register Zero GPIOR0[7:0] */ #define GPIOR0 _SFR_IO8(0x13) /* ATtiny General Purpose I/O Register One GPIOR1[7:0] */ #define GPIOR1 _SFR_IO8(0x14) /* ATtiny General Purpose I/O Register Two One GPIOR2[7:0] */ #define GPIOR2 _SFR_IO8(0x15) /* Input Pins, Port B PORTB[7:0] */ #define PINB _SFR_IO8(0x16) #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* Data Direction Register, Port B PORTB[7:0] */ #define DDRB _SFR_IO8(0x17) #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* Data Register, Port B PORTB[7:0] */ #define PORTB _SFR_IO8(0x18) #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* Port A Input Pins Address PINA[2:0] */ #define PINA _SFR_IO8(0x19) #define PINA2 2 #define PINA1 1 #define PINA0 0 /* Port A Data Direction Register DDRA[2:0] */ #define DDRA _SFR_IO8(0x1A) #define DDRA2 2 #define DDRA1 1 #define DDRA0 0 /* Port A Data Register PORTA[2:0] */ #define PORTA _SFR_IO8(0x1B) #define PA2 2 #define PA1 1 #define PA0 0 /* ATtiny EEPROM Control Register EECR */ #define EECR _SFR_IO8(0x1C) #define EEPM1 5 #define EEPM0 4 #define EERIE 3 #define EEMPE 2 #define EEPE 1 #define EERE 0 /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* The EEPROM Address Register EEAR[6:0] */ #define EEAR _SFR_IO8(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEAR6 6 #define EEAR5 5 #define EEAR4 4 #define EEAR3 3 #define EEAR2 2 #define EEAR1 1 #define EEAR0 0 /* 0x1F Reserved */ /* ATtiny Pin Change Mask Register PCMSK PCINT[7:0] */ #define PCMSK _SFR_IO8(0x20) #define PCINT7 7 #define PCINT6 6 #define PCINT5 5 #define PCINT4 4 #define PCINT3 3 #define PCINT2 2 #define PCINT1 1 #define PCINT0 0 /* ATtiny Watchdog Timer Control Register WDTCSR */ #define WDTCSR _SFR_IO8(0x21) #define WDIF 7 #define WDIE 6 #define WDP3 5 #define WDCE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* ATtiny Timer/Counter1 Control Register C TCCR1C */ #define TCCR1C _SFR_IO8(0x22) #define FOC1A 7 #define FOC1B 6 /* General Timer/Counter Control Register GTCCR */ #define GTCCR _SFR_IO8(0x23) #define PSR10 0 /* T/C 1 Input Capture Register ICR1[15:0] */ #define ICR1 _SFR_IO16(0x24) #define ICR1L _SFR_IO8(0x24) #define ICR1H _SFR_IO8(0x25) /* ATtiny Clock Prescale Register */ #define CLKPR _SFR_IO8(0x26) #define CLKPCE 7 #define CLKPS3 3 #define CLKPS2 2 #define CLKPS1 1 #define CLKPS0 0 /* 0x27 Reserved */ /* ATtiny Output Compare Register 1 B OCR1B[15:0] */ #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) /* Output Compare Register 1 OCR1A[15:0] */ #define OCR1 _SFR_IO16(0x2A) #define OCR1L _SFR_IO8(0x2A) #define OCR1H _SFR_IO8(0x2B) #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) /* Timer/Counter 1 TCNT1[15:0] */ #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) /* ATtiny Timer/Counter 1 Control and Status Register TCCR1B */ #define TCCR1B _SFR_IO8(0x2E) #define ICNC1 7 #define ICES1 6 #define WGM13 4 #define WGM12 3 /* Was CTC1 in AT90S2313 */ #define CS12 2 #define CS11 1 #define CS10 0 /* ATtiny Timer/Counter 1 Control Register TCCR1A */ #define TCCR1A _SFR_IO8(0x2F) #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define WGM11 1 /* Was PWM11 in AT90S2313 */ #define WGM10 0 /* Was PWM10 in AT90S2313 */ /* ATtiny Timer/Counter Control Register A TCCR0A */ #define TCCR0A _SFR_IO8(0x30) #define COM0A1 7 #define COM0A0 6 #define COM0B1 5 #define COM0B0 4 #define WGM01 1 #define WGM00 0 /* ATtiny Oscillator Calibration Register OSCCAL[6:0] */ #define OSCCAL _SFR_IO8(0x31) #define CAL6 6 #define CAL5 5 #define CAL4 4 #define CAL3 3 #define CAL2 2 #define CAL1 1 #define CAL0 0 /* Timer/Counter 0 TCNT0[7:0] */ #define TCNT0 _SFR_IO8(0x32) /* ATtiny Timer/Counter 0 Control Register TCCR0B */ #define TCCR0B _SFR_IO8(0x33) #define FOC0A 7 #define FOC0B 6 #define WGM02 3 #define CS02 2 #define CS01 1 #define CS00 0 /* ATtiny MCU Status Register MCUSR */ #define MCUSR _SFR_IO8(0x34) #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 /* ATtiny MCU general Control Register MCUCR */ #define MCUCR _SFR_IO8(0x35) #define PUD 7 #define SM1 6 #define SE 5 #define SM0 4 /* Some preliminary ATtiny2313 data sheets incorrectly refer to this bit as SMD; was SM in AT90S2313. */ #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* ATtiny Output Compare Register A OCR0A[7:0] */ #define OCR0A _SFR_IO8(0x36) /* ATtiny Store Program Memory Control and Status Register SPMCSR */ #define SPMCSR _SFR_IO8(0x37) #define CTPB 4 #define RFLB 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 /* The name is used in ATtiny2313.xml file. */ #define SELFPRGEN 0 /* The name is used in datasheet. */ #define SELFPRGE 0 /* The name is left for compatibility. */ /* ATtiny Timer/Counter Interrupt Flag register TIFR */ #define TIFR _SFR_IO8(0x38) #define TOV1 7 #define OCF1A 6 #define OCF1B 5 #define ICF1 3 #define OCF0B 2 #define TOV0 1 #define OCF0A 0 /* ATtiny Timer/Counter Interrupt MaSK register TIMSK */ #define TIMSK _SFR_IO8(0x39) #define TOIE1 7 #define OCIE1A 6 #define OCIE1B 5 #define ICIE1 3 #define OCIE0B 2 #define TOIE0 1 #define OCIE0A 0 /* ATtiny External Interrupt Flag Register EIFR, was GIFR */ #define EIFR _SFR_IO8(0x3A) #define INTF1 7 #define INTF0 6 #define PCIF 5 /* ATtiny General Interrupt MaSK register GIMSK */ #define GIMSK _SFR_IO8(0x3B) #define INT1 7 #define INT0 6 #define PCIE 5 /* ATtiny Output Compare Register B OCR0B[7:0] */ #define OCR0B _SFR_IO8(0x3C) /* Interrupt vectors: */ /* External Interrupt Request 0 */ #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) #define SIG_INT0 _VECTOR(1) /* External Interrupt Request 1 */ #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) #define SIG_INT1 _VECTOR(2) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect _VECTOR(3) #define SIG_INPUT_CAPTURE1 _VECTOR(3) #define SIG_TIMER1_CAPT _VECTOR(3) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE1A _VECTOR(4) #define SIG_TIMER1_COMPA _VECTOR(4) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect _VECTOR(5) #define SIG_OVERFLOW1 _VECTOR(5) #define SIG_TIMER1_OVF _VECTOR(5) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect _VECTOR(6) #define SIG_OVERFLOW0 _VECTOR(6) #define SIG_TIMER0_OVF _VECTOR(6) /* USART, Rx Complete */ #define USART_RX_vect _VECTOR(7) #define SIG_USART0_RECV _VECTOR(7) #define SIG_USART0_RX _VECTOR(7) /* USART Data Register Empty */ #define USART_UDRE_vect _VECTOR(8) #define SIG_USART0_DATA _VECTOR(8) #define SIG_USART0_UDRE _VECTOR(8) /* USART, Tx Complete */ #define USART_TX_vect _VECTOR(9) #define SIG_USART0_TRANS _VECTOR(9) #define SIG_USART0_TX _VECTOR(9) /* Analog Comparator */ #define ANA_COMP_vect _VECTOR(10) #define SIG_COMPARATOR _VECTOR(10) #define SIG_ANALOG_COMP _VECTOR(10) #define PCINT_vect _VECTOR(11) #define SIG_PIN_CHANGE _VECTOR(11) #define SIG_PCINT _VECTOR(11) #define TIMER1_COMPB_vect _VECTOR(12) #define SIG_OUTPUT_COMPARE1B _VECTOR(12) #define SIG_TIMER1_COMPB _VECTOR(12) #define TIMER0_COMPA_vect _VECTOR(13) #define SIG_OUTPUT_COMPARE0A _VECTOR(13) #define SIG_TIMER0_COMPA _VECTOR(13) #define TIMER0_COMPB_vect _VECTOR(14) #define SIG_OUTPUT_COMPARE0B _VECTOR(14) #define SIG_TIMER0_COMPB _VECTOR(14) /* USI Start Condition */ #define USI_START_vect _VECTOR(15) #define SIG_USI_START _VECTOR(15) #define SIG_USI_START _VECTOR(15) /* USI Overflow */ #define USI_OVERFLOW_vect _VECTOR(16) #define SIG_USI_OVERFLOW _VECTOR(16) #define SIG_USI_OVERFLOW _VECTOR(16) #define EEPROM_READY_vect _VECTOR(17) #define SIG_EEPROM_READY _VECTOR(17) #define SIG_EE_READY _VECTOR(17) /* Watchdog Timer Overflow */ #define WDT_OVERFLOW_vect _VECTOR(18) #define SIG_WATCHDOG_TIMEOUT _VECTOR(18) #define SIG_WDT_OVERFLOW _VECTOR(18) /* 38 = (18*2)+2: Number of vectors times two, plus the reset vector */ #define _VECTORS_SIZE 38 /* Constants */ #define SPM_PAGESIZE 32 #define RAMEND 0xDF #define XRAMEND RAMEND #define E2END 0x7F #define E2PAGESIZE 4 #define FLASHEND 0x07FF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL1 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_RSTDISBL (unsigned char)~_BV(0) #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) #define FUSE_BODLEVEL2 (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_EESAVE (unsigned char)~_BV(6) #define FUSE_DWEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x91 #define SIGNATURE_2 0x0A #endif /* _AVR_IOTN2313_H_ */

[tn2313def.inc]	[iotn2313.h]
;*** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT **************** ;* Created: 2009-11-03 14:40 *** Source: ATtiny2313.xml ****** ;*********************************************************************** ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y ;* ;* Number : AVR000 ;* File Name : "tn2313def.inc" ;* Title : Register/Bit Definitions for the ATtiny2313 ;* Date : 2009-11-03 ;* Version : 2.35 ;* Support E-mail : avr@atmel.com ;* Target MCU : ATtiny2313 ;* ;* DESCRIPTION ;* When including this file in the assembly program file, all I/O register ;* names and I/O register bit names appearing in the data book can be used. ;* In addition, the six registers forming the three data pointers X, Y and ;* Z have been assigned names XL - ZH. Highest RAM address for Internal ;* SRAM is also defined ;* ;* The Register names are represented by their hexadecimal address. ;* ;* The Register Bit names are represented by their bit number (0-7). ;* ;* Please observe the difference in using the bit names with instructions ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" ;* (skip if bit in register set/cleared). The following example illustrates ;* this: ;* ;* in r16,PORTB ;read PORTB latch ;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) ;* out PORTB,r16 ;output to PORTB ;* ;* in r16,TIFR ;read the Timer Interrupt Flag Register ;* sbrc r16,TOV0 ;test the overflow flag (use bit#) ;* rjmp TOV0_is_set ;jump if set ;* ... ;otherwise do something else ;*********************************************************************** #ifndef _TN2313DEF_INC_ #define _TN2313DEF_INC_ #pragma partinc 0 ; * SPECIFY DEVICE *********************************************** .device ATtiny2313 #pragma AVRPART ADMIN PART_NAME ATtiny2313 .equ SIGNATURE_000 = 0x1e .equ SIGNATURE_001 = 0x91 .equ SIGNATURE_002 = 0x0a #pragma AVRPART CORE CORE_VERSION V2 #pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z+ ; * I/O REGISTER DEFINITIONS ************************************* ; NOTE: ; Definitions marked "MEMORY MAPPED"are extended I/O ports ; and cannot be used with IN/OUT instructions .equ SREG = 0x3f .equ SPL = 0x3d .equ OCR0B = 0x3c .equ GIMSK = 0x3b .equ EIFR = 0x3a .equ TIMSK = 0x39 .equ TIFR = 0x38 .equ SPMCSR = 0x37 .equ OCR0A = 0x36 .equ MCUCR = 0x35 .equ MCUSR = 0x34 .equ TCCR0B = 0x33 .equ TCNT0 = 0x32 .equ OSCCAL = 0x31 .equ TCCR0A = 0x30 .equ TCCR1A = 0x2f .equ TCCR1B = 0x2e .equ TCNT1L = 0x2c .equ TCNT1H = 0x2d .equ OCR1AL = 0x2a .equ OCR1AH = 0x2b .equ OCR1BL = 0x28 .equ OCR1BH = 0x29 .equ CLKPR = 0x26 .equ ICR1L = 0x24 .equ ICR1H = 0x25 .equ GTCCR = 0x23 .equ TCCR1C = 0x22 .equ WDTCR = 0x21 .equ PCMSK = 0x20 .equ EEAR = 0x1e .equ EEDR = 0x1d .equ EECR = 0x1c .equ PORTA = 0x1b .equ DDRA = 0x1a .equ PINA = 0x19 .equ PORTB = 0x18 .equ DDRB = 0x17 .equ PINB = 0x16 .equ GPIOR2 = 0x15 .equ GPIOR1 = 0x14 .equ GPIOR0 = 0x13 .equ PORTD = 0x12 .equ DDRD = 0x11 .equ PIND = 0x10 .equ USIDR = 0x0f .equ USISR = 0x0e .equ USICR = 0x0d .equ UDR = 0x0c .equ UCSRA = 0x0b .equ UCSRB = 0x0a .equ UBRRL = 0x09 .equ ACSR = 0x08 .equ UCSRC = 0x03 .equ UBRRH = 0x02 .equ DIDR = 0x01 ; * BIT DEFINITIONS ********************************************** ; * PORTB ******************** ; PORTB - Port B Data Register .equ PORTB0 = 0 ; Port B Data Register bit 0 .equ PB0 = 0 ; For compatibility .equ PORTB1 = 1 ; Port B Data Register bit 1 .equ PB1 = 1 ; For compatibility .equ PORTB2 = 2 ; Port B Data Register bit 2 .equ PB2 = 2 ; For compatibility .equ PORTB3 = 3 ; Port B Data Register bit 3 .equ PB3 = 3 ; For compatibility .equ PORTB4 = 4 ; Port B Data Register bit 4 .equ PB4 = 4 ; For compatibility .equ PORTB5 = 5 ; Port B Data Register bit 5 .equ PB5 = 5 ; For compatibility .equ PORTB6 = 6 ; Port B Data Register bit 6 .equ PB6 = 6 ; For compatibility .equ PORTB7 = 7 ; Port B Data Register bit 7 .equ PB7 = 7 ; For compatibility ; DDRB - Port B Data Direction Register .equ DDB0 = 0 ; Port B Data Direction Register bit 0 .equ DDB1 = 1 ; Port B Data Direction Register bit 1 .equ DDB2 = 2 ; Port B Data Direction Register bit 2 .equ DDB3 = 3 ; Port B Data Direction Register bit 3 .equ DDB4 = 4 ; Port B Data Direction Register bit 4 .equ DDB5 = 5 ; Port B Data Direction Register bit 5 .equ DDB6 = 6 ; Port B Data Direction Register bit 6 .equ DDB7 = 7 ; Port B Data Direction Register bit 7 ; PINB - Port B Input Pins .equ PINB0 = 0 ; Port B Input Pins bit 0 .equ PINB1 = 1 ; Port B Input Pins bit 1 .equ PINB2 = 2 ; Port B Input Pins bit 2 .equ PINB3 = 3 ; Port B Input Pins bit 3 .equ PINB4 = 4 ; Port B Input Pins bit 4 .equ PINB5 = 5 ; Port B Input Pins bit 5 .equ PINB6 = 6 ; Port B Input Pins bit 6 .equ PINB7 = 7 ; Port B Input Pins bit 7 ; * TIMER_COUNTER_0 ********** ; TIMSK - Timer/Counter Interrupt Mask Register .equ OCIE0A = 0 ; Timer/Counter0 Output Compare Match A Interrupt Enable .equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable .equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable ; TIFR - Timer/Counter Interrupt Flag register .equ OCF0A = 0 ; Timer/Counter0 Output Compare Flag 0A .equ TOV0 = 1 ; Timer/Counter0 Overflow Flag .equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B ; OCR0B - Timer/Counter0 Output Compare Register .equ OCR0_0 = 0 ; .equ OCR0_1 = 1 ; .equ OCR0_2 = 2 ; .equ OCR0_3 = 3 ; .equ OCR0_4 = 4 ; .equ OCR0_5 = 5 ; .equ OCR0_6 = 6 ; .equ OCR0_7 = 7 ; ; OCR0A - Timer/Counter0 Output Compare Register .equ OCR0A_0 = 0 ; .equ OCR0A_1 = 1 ; .equ OCR0A_2 = 2 ; .equ OCR0A_3 = 3 ; .equ OCR0A_4 = 4 ; .equ OCR0A_5 = 5 ; .equ OCR0A_6 = 6 ; .equ OCR0A_7 = 7 ; ; TCCR0A - Timer/Counter Control Register A .equ WGM00 = 0 ; Waveform Generation Mode .equ WGM01 = 1 ; Waveform Generation Mode .equ COM0B0 = 4 ; Compare Match Output B Mode .equ COM0B1 = 5 ; Compare Match Output B Mode .equ COM0A0 = 6 ; Compare Match Output A Mode .equ COM0A1 = 7 ; Compare Match Output A Mode ; TCNT0 - Timer/Counter0 .equ TCNT0_0 = 0 ; .equ TCNT0_1 = 1 ; .equ TCNT0_2 = 2 ; .equ TCNT0_3 = 3 ; .equ TCNT0_4 = 4 ; .equ TCNT0_5 = 5 ; .equ TCNT0_6 = 6 ; .equ TCNT0_7 = 7 ; ; TCCR0B - Timer/Counter Control Register B .equ TCCR0 = TCCR0B ; For compatibility .equ CS00 = 0 ; Clock Select .equ CS01 = 1 ; Clock Select .equ CS02 = 2 ; Clock Select .equ WGM02 = 3 ; .equ FOC0B = 6 ; Force Output Compare B .equ FOC0A = 7 ; Force Output Compare B ; * TIMER_COUNTER_1 ********** ; TIMSK - Timer/Counter Interrupt Mask Register .equ ICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable .equ TICIE = ICIE1 ; For compatibility .equ OCIE1B = 5 ; Timer/Counter1 Output CompareB Match Interrupt Enable .equ OCIE1A = 6 ; Timer/Counter1 Output CompareA Match Interrupt Enable .equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable ; TIFR - Timer/Counter Interrupt Flag register .equ ICF1 = 3 ; Input Capture Flag 1 .equ OCF1B = 5 ; Output Compare Flag 1B .equ OCF1A = 6 ; Output Compare Flag 1A .equ TOV1 = 7 ; Timer/Counter1 Overflow Flag ; TCCR1A - Timer/Counter1 Control Register A .equ WGM10 = 0 ; Pulse Width Modulator Select Bit 0 .equ PWM10 = WGM10 ; For compatibility .equ WGM11 = 1 ; Pulse Width Modulator Select Bit 1 .equ PWM11 = WGM11 ; For compatibility .equ COM1B0 = 4 ; Comparet Ouput Mode 1B, bit 0 .equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 .equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0 .equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 ; TCCR1B - Timer/Counter1 Control Register B .equ CS10 = 0 ; Clock Select bit 0 .equ CS11 = 1 ; Clock Select 1 bit 1 .equ CS12 = 2 ; Clock Select1 bit 2 .equ WGM12 = 3 ; Waveform Generation Mode Bit 2 .equ CTC1 = WGM12 ; For compatibility .equ WGM13 = 4 ; Waveform Generation Mode Bit 3 .equ ICES1 = 6 ; Input Capture 1 Edge Select .equ ICNC1 = 7 ; Input Capture 1 Noise Canceler ; TCCR1C - Timer/Counter1 Control Register C .equ FOC1B = 6 ; Force Output Compare for Channel B .equ FOC1A = 7 ; Force Output Compare for Channel A ; * WATCHDOG ***************** ; WDTCR - Watchdog Timer Control Register .equ WDTCSR = WDTCR ; For compatibility .equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 .equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 .equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 .equ WDE = 3 ; Watch Dog Enable .equ WDCE = 4 ; Watchdog Change Enable .equ WDTOE = WDCE ; For compatibility .equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3 .equ WDIE = 6 ; Watchdog Timeout Interrupt Enable .equ WDIF = 7 ; Watchdog Timeout Interrupt Flag ; * EXTERNAL_INTERRUPT ******* ; GIMSK - General Interrupt Mask Register .equ PCIE = 5 ; .equ INT0 = 6 ; External Interrupt Request 0 Enable .equ INT1 = 7 ; External Interrupt Request 1 Enable ; EIFR - Extended Interrupt Flag Register .equ GIFR = EIFR ; For compatibility .equ PCIF = 5 ; .equ INTF0 = 6 ; External Interrupt Flag 0 .equ INTF1 = 7 ; External Interrupt Flag 1 ; * USART ******************** ; UDR - USART I/O Data Register .equ UDR0 = 0 ; USART I/O Data Register bit 0 .equ UDR1 = 1 ; USART I/O Data Register bit 1 .equ UDR2 = 2 ; USART I/O Data Register bit 2 .equ UDR3 = 3 ; USART I/O Data Register bit 3 .equ UDR4 = 4 ; USART I/O Data Register bit 4 .equ UDR5 = 5 ; USART I/O Data Register bit 5 .equ UDR6 = 6 ; USART I/O Data Register bit 6 .equ UDR7 = 7 ; USART I/O Data Register bit 7 ; UCSRA - USART Control and Status Register A .equ USR = UCSRA ; For compatibility .equ MPCM = 0 ; Multi-processor Communication Mode .equ U2X = 1 ; Double the USART Transmission Speed .equ UPE = 2 ; USART Parity Error .equ PE = UPE ; For compatibility .equ DOR = 3 ; Data overRun .equ FE = 4 ; Framing Error .equ UDRE = 5 ; USART Data Register Empty .equ TXC = 6 ; USART Transmitt Complete .equ RXC = 7 ; USART Receive Complete ; UCSRB - USART Control and Status Register B .equ UCR = UCSRB ; For compatibility .equ TXB8 = 0 ; Transmit Data Bit 8 .equ RXB8 = 1 ; Receive Data Bit 8 .equ UCSZ2 = 2 ; Character Size .equ CHR9 = UCSZ2 ; For compatibility .equ TXEN = 3 ; Transmitter Enable .equ RXEN = 4 ; Receiver Enable .equ UDRIE = 5 ; USART Data register Empty Interrupt Enable .equ TXCIE = 6 ; TX Complete Interrupt Enable .equ RXCIE = 7 ; RX Complete Interrupt Enable ; UCSRC - USART Control and Status Register C .equ UCPOL = 0 ; Clock Polarity .equ UCSZ0 = 1 ; Character Size Bit 0 .equ UCSZ1 = 2 ; Character Size Bit 1 .equ USBS = 3 ; Stop Bit Select .equ UPM0 = 4 ; Parity Mode Bit 0 .equ UPM1 = 5 ; Parity Mode Bit 1 .equ UMSEL = 6 ; USART Mode Select .equ UBRR = UBRRL ; For compatibility ; * ANALOG_COMPARATOR ******** ; ACSR - Analog Comparator Control And Status Register .equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 .equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 .equ ACIC = 2 ; .equ ACIE = 3 ; Analog Comparator Interrupt Enable .equ ACI = 4 ; Analog Comparator Interrupt Flag .equ ACO = 5 ; Analog Compare Output .equ ACBG = 6 ; Analog Comparator Bandgap Select .equ ACD = 7 ; Analog Comparator Disable ; DIDR - Digital Input Disable Register 1 .equ AIN0D = 0 ; AIN0 Digital Input Disable .equ AIN1D = 1 ; AIN1 Digital Input Disable ; * PORTD ******************** ; PORTD - Data Register, Port D .equ PORTD0 = 0 ; .equ PD0 = 0 ; For compatibility .equ PORTD1 = 1 ; .equ PD1 = 1 ; For compatibility .equ PORTD2 = 2 ; .equ PD2 = 2 ; For compatibility .equ PORTD3 = 3 ; .equ PD3 = 3 ; For compatibility .equ PORTD4 = 4 ; .equ PD4 = 4 ; For compatibility .equ PORTD5 = 5 ; .equ PD5 = 5 ; For compatibility .equ PORTD6 = 6 ; .equ PD6 = 6 ; For compatibility ; DDRD - Data Direction Register, Port D .equ DDD0 = 0 ; .equ DDD1 = 1 ; .equ DDD2 = 2 ; .equ DDD3 = 3 ; .equ DDD4 = 4 ; .equ DDD5 = 5 ; .equ DDD6 = 6 ; ; PIND - Input Pins, Port D .equ PIND0 = 0 ; .equ PIND1 = 1 ; .equ PIND2 = 2 ; .equ PIND3 = 3 ; .equ PIND4 = 4 ; .equ PIND5 = 5 ; .equ PIND6 = 6 ; ; * EEPROM ******************* ; EEAR - EEPROM Read/Write Access .equ EEARL = EEAR ; For compatibility .equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0 .equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1 .equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2 .equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3 .equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4 .equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5 .equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6 ; EEDR - EEPROM Data Register .equ EEDR0 = 0 ; EEPROM Data Register bit 0 .equ EEDR1 = 1 ; EEPROM Data Register bit 1 .equ EEDR2 = 2 ; EEPROM Data Register bit 2 .equ EEDR3 = 3 ; EEPROM Data Register bit 3 .equ EEDR4 = 4 ; EEPROM Data Register bit 4 .equ EEDR5 = 5 ; EEPROM Data Register bit 5 .equ EEDR6 = 6 ; EEPROM Data Register bit 6 .equ EEDR7 = 7 ; EEPROM Data Register bit 7 ; EECR - EEPROM Control Register .equ EERE = 0 ; EEPROM Read Enable .equ EEPE = 1 ; EEPROM Write Enable .equ EEWE = EEPE ; For compatibility .equ EEMPE = 2 ; EEPROM Master Write Enable .equ EEMWE = EEMPE ; For compatibility .equ EERIE = 3 ; EEProm Ready Interrupt Enable .equ EEPM0 = 4 ; .equ EEPM1 = 5 ; ; * PORTA ******************** ; PORTA - Port A Data Register .equ PORTA0 = 0 ; Port A Data Register bit 0 .equ PA0 = 0 ; For compatibility .equ PORTA1 = 1 ; Port A Data Register bit 1 .equ PA1 = 1 ; For compatibility .equ PORTA2 = 2 ; Port A Data Register bit 2 .equ PA2 = 2 ; For compatibility ; DDRA - Port A Data Direction Register .equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 .equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 .equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 ; PINA - Port A Input Pins .equ PINA0 = 0 ; Input Pins, Port A bit 0 .equ PINA1 = 1 ; Input Pins, Port A bit 1 .equ PINA2 = 2 ; Input Pins, Port A bit 2 ; * CPU ********************** ; SREG - Status Register .equ SREG_C = 0 ; Carry Flag .equ SREG_Z = 1 ; Zero Flag .equ SREG_N = 2 ; Negative Flag .equ SREG_V = 3 ; Two's Complement Overflow Flag .equ SREG_S = 4 ; Sign Bit .equ SREG_H = 5 ; Half Carry Flag .equ SREG_T = 6 ; Bit Copy Storage .equ SREG_I = 7 ; Global Interrupt Enable ; SPMCSR - Store Program Memory Control and Status register .equ SPMEN = 0 ; Store Program Memory Enable .equ PGERS = 1 ; Page Erase .equ PGWRT = 2 ; Page Write .equ RFLB = 3 ; Read Fuse and Lock Bits .equ CTPB = 4 ; Clear Temporary Page Buffer ; MCUCR - MCU Control Register .equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 .equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 .equ ISC10 = 2 ; Interrupt Sense Control 1 bit 0 .equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1 .equ SM0 = 4 ; Sleep Mode Select Bit 0 .equ SM = SM0 ; For compatibility .equ SE = 5 ; Sleep Enable .equ SM1 = 6 ; Sleep Mode Select Bit 1 .equ PUD = 7 ; Pull-up Disable ; CLKPR - Clock Prescale Register .equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 .equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 .equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 .equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 .equ CLKPCE = 7 ; Clock Prescaler Change Enable ; MCUSR - MCU Status register .equ PORF = 0 ; Power-On Reset Flag .equ EXTRF = 1 ; External Reset Flag .equ BORF = 2 ; Brown-out Reset Flag .equ WDRF = 3 ; Watchdog Reset Flag ; OSCCAL - Oscillator Calibration Register .equ CAL0 = 0 ; Oscillatro Calibration Value Bit 0 .equ CAL1 = 1 ; Oscillatro Calibration Value Bit 1 .equ CAL2 = 2 ; Oscillatro Calibration Value Bit 2 .equ CAL3 = 3 ; Oscillatro Calibration Value Bit 3 .equ CAL4 = 4 ; Oscillatro Calibration Value Bit 4 .equ CAL5 = 5 ; Oscillatro Calibration Value Bit 5 .equ CAL6 = 6 ; Oscillatro Calibration Value Bit 6 ; GTCCR - General Timer Counter Control Register .equ SFIOR = GTCCR ; For compatibility .equ PSR10 = 0 ; ; PCMSK - Pin-Change Mask register .equ PCINT0 = 0 ; Pin-Change Interrupt 0 .equ PCINT1 = 1 ; Pin-Change Interrupt 1 .equ PCINT2 = 2 ; Pin-Change Interrupt 2 .equ PCINT3 = 3 ; Pin-Change Interrupt 3 .equ PCINT4 = 4 ; Pin-Change Interrupt 4 .equ PCINT5 = 5 ; Pin-Change Interrupt 5 .equ PCINT6 = 6 ; Pin-Change Interrupt 6 .equ PCINT7 = 7 ; Pin-Change Interrupt 7 ; GPIOR2 - General Purpose I/O Register 2 .equ GPIOR20 = 0 ; General Purpose I/O Register 2 bit 0 .equ GPIOR21 = 1 ; General Purpose I/O Register 2 bit 1 .equ GPIOR22 = 2 ; General Purpose I/O Register 2 bit 2 .equ GPIOR23 = 3 ; General Purpose I/O Register 2 bit 3 .equ GPIOR24 = 4 ; General Purpose I/O Register 2 bit 4 .equ GPIOR25 = 5 ; General Purpose I/O Register 2 bit 5 .equ GPIOR26 = 6 ; General Purpose I/O Register 2 bit 6 .equ GPIOR27 = 7 ; General Purpose I/O Register 2 bit 7 ; GPIOR1 - General Purpose I/O Register 1 .equ GPIOR10 = 0 ; General Purpose I/O Register 1 bit 0 .equ GPIOR11 = 1 ; General Purpose I/O Register 1 bit 1 .equ GPIOR12 = 2 ; General Purpose I/O Register 1 bit 2 .equ GPIOR13 = 3 ; General Purpose I/O Register 1 bit 3 .equ GPIOR14 = 4 ; General Purpose I/O Register 1 bit 4 .equ GPIOR15 = 5 ; General Purpose I/O Register 1 bit 5 .equ GPIOR16 = 6 ; General Purpose I/O Register 1 bit 6 .equ GPIOR17 = 7 ; General Purpose I/O Register 1 bit 7 ; GPIOR0 - General Purpose I/O Register 0 .equ GPIOR00 = 0 ; General Purpose I/O Register 0 bit 0 .equ GPIOR01 = 1 ; General Purpose I/O Register 0 bit 1 .equ GPIOR02 = 2 ; General Purpose I/O Register 0 bit 2 .equ GPIOR03 = 3 ; General Purpose I/O Register 0 bit 3 .equ GPIOR04 = 4 ; General Purpose I/O Register 0 bit 4 .equ GPIOR05 = 5 ; General Purpose I/O Register 0 bit 5 .equ GPIOR06 = 6 ; General Purpose I/O Register 0 bit 6 .equ GPIOR07 = 7 ; General Purpose I/O Register 0 bit 7 ; * USI ********************** ; USIDR - USI Data Register .equ USIDR0 = 0 ; USI Data Register bit 0 .equ USIDR1 = 1 ; USI Data Register bit 1 .equ USIDR2 = 2 ; USI Data Register bit 2 .equ USIDR3 = 3 ; USI Data Register bit 3 .equ USIDR4 = 4 ; USI Data Register bit 4 .equ USIDR5 = 5 ; USI Data Register bit 5 .equ USIDR6 = 6 ; USI Data Register bit 6 .equ USIDR7 = 7 ; USI Data Register bit 7 ; USISR - USI Status Register .equ USICNT0 = 0 ; USI Counter Value Bit 0 .equ USICNT1 = 1 ; USI Counter Value Bit 1 .equ USICNT2 = 2 ; USI Counter Value Bit 2 .equ USICNT3 = 3 ; USI Counter Value Bit 3 .equ USIDC = 4 ; Data Output Collision .equ USIPF = 5 ; Stop Condition Flag .equ USIOIF = 6 ; Counter Overflow Interrupt Flag .equ USISIF = 7 ; Start Condition Interrupt Flag ; USICR - USI Control Register .equ USITC = 0 ; Toggle Clock Port Pin .equ USICLK = 1 ; Clock Strobe .equ USICS0 = 2 ; USI Clock Source Select Bit 0 .equ USICS1 = 3 ; USI Clock Source Select Bit 1 .equ USIWM0 = 4 ; USI Wire Mode Bit 0 .equ USIWM1 = 5 ; USI Wire Mode Bit 1 .equ USIOIE = 6 ; Counter Overflow Interrupt Enable .equ USISIE = 7 ; Start Condition Interrupt Enable ; * LOCKSBITS **************************************************** .equ LB1 = 0 ; Lockbit .equ LB2 = 1 ; Lockbit ; * FUSES ******************************************************** ; LOW fuse bits .equ CKSEL0 = 0 ; Select Clock Source .equ CKSEL1 = 1 ; Select Clock Source .equ CKSEL2 = 2 ; Select Clock Source .equ CKSEL3 = 3 ; Select Clock Source .equ SUT0 = 4 ; Select start-up time .equ SUT1 = 5 ; Select start-up time .equ CKOUT = 6 ; Clock output .equ CKDIV8 = 7 ; Divide clock by 8 ; HIGH fuse bits .equ BODLEVEL0 = 0 ; Brown-out Detector trigger level .equ BODLEVEL1 = 1 ; Brown-out Detector trigger level .equ BODLEVEL2 = 2 ; Brown-out Detector trigger level .equ EESAVE = 3 ; EEPROM memory is preserved through chip erase .equ WDTON = 4 ; Watchdog Timer Always On .equ SPIEN = 5 ; Enable Serial programming and Data Downloading .equ DWEN = 6 ; debugWIRE Enable .equ RSTDISBL = 7 ; External reset disable ; EXTENDED fuse bits .equ SELFPRGEN = 0 ; Self Programming Enable ; * CPU REGISTER DEFINITIONS ************************************* .def XH = r27 .def XL = r26 .def YH = r29 .def YL = r28 .def ZH = r31 .def ZL = r30 ; * DATA MEMORY DECLARATIONS ************************************* .equ FLASHEND = 0x03ff ; Note: Word address .equ IOEND = 0x003f .equ SRAM_START = 0x0060 .equ SRAM_SIZE = 128 .equ RAMEND = 0x00df .equ XRAMEND = 0x0000 .equ E2END = 0x007f .equ EEPROMEND = 0x007f .equ EEADRBITS = 7 #pragma AVRPART MEMORY PROG_FLASH 2048 #pragma AVRPART MEMORY EEPROM 128 #pragma AVRPART MEMORY INT_SRAM SIZE 128 #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 ; * BOOTLOADER DECLARATIONS ************************************** .equ NRWW_START_ADDR = 0x0 .equ NRWW_STOP_ADDR = 0x3ff .equ RWW_START_ADDR = 0x0 .equ RWW_STOP_ADDR = 0x0 .equ PAGESIZE = 16 ; * INTERRUPT VECTORS ********************************************** .equ INT0addr = 0x0001 ; External Interrupt Request 0 .equ INT1addr = 0x0002 ; External Interrupt Request 1 .equ ICP1addr = 0x0003 ; Timer/Counter1 Capture Event .equ OC1Aaddr = 0x0004 ; Timer/Counter1 Compare Match A .equ OC1addr = 0x0004 ; For compatibility .equ OVF1addr = 0x0005 ; Timer/Counter1 Overflow .equ OVF0addr = 0x0006 ; Timer/Counter0 Overflow .equ URXCaddr = 0x0007 ; USART, Rx Complete .equ URXC0addr = 0x0007 ; For compatibility .equ UDREaddr = 0x0008 ; USART Data Register Empty .equ UDRE0addr = 0x0008 ; For compatibility .equ UTXCaddr = 0x0009 ; USART, Tx Complete .equ UTXC0addr = 0x0009 ; For compatibility .equ ACIaddr = 0x000a ; Analog Comparator .equ PCIaddr = 0x000b ; .equ OC1Baddr = 0x000c ; .equ OC0Aaddr = 0x000d ; .equ OC0Baddr = 0x000e ; .equ USI_STARTaddr = 0x000f ; USI Start Condition .equ USI_OVFaddr = 0x0010 ; USI Overflow .equ ERDYaddr = 0x0011 ; .equ WDTaddr = 0x0012 ; Watchdog Timer Overflow .equ INT_VECTORS_SIZE = 19 ; size in words #endif /* _TN2313DEF_INC_ / ; ** END OF FILE ****************************************************	/* Copyright (c) 2004, 2005, 2006 Bob Paddock All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. / / $Id: iotn2313.h,v 1.14.2.8 2009/02/11 18:44:42 arcanum Exp $ / / iotn2313.h derived from io2313.h by Bob Paddock. The changes between the AT90S2313 and the ATtiny2313 are extensive. Atmel has renamed several registers, and bits. See Atmel application note AVR091, as well as the errata at the end of the current ATtiny2313 data sheet. Some of the names have changed more than once during the sampling period of the ATtiny2313. Where there is no conflict the new and old names are both supported. In the case of a new feature in a register, only the new name is used. This intentionally breaks old code, so that there are no silent bugs. The source code must be updated to the new name in this case. The hardware interrupt vector table has changed from that of the AT90S2313. ATtiny2313 programs in page mode rather than the byte mode of the AT90S2313. Beware of programming the ATtiny2313 as a AT90S2313 device, when programming the Flash. ATtiny2313 has Signature Bytes: 0x1E 0x91 0x0A. Changes and/or additions are noted by "ATtiny" in the comments below. / / avr/iotn2313.h - definitions for ATtiny2313 / #ifndef _AVR_IOTN2313_H_ #define _AVR_IOTN2313_H_ 1 / This file should only be included from <avr/io.h>, never directly. / #ifndef _AVR_IO_H_ # error "Include <avr/io.h> instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn2313.h" #else # error "Attempt to include more than one <avr/ioXXX.h> file." #endif / I/O registers / / * The Register Bit names are represented by their bit number (0-7). * Example: PORTB \|= _BV(PORTB7); Set MSB of PORTB. / / 0x00 Reserved / / ATtiny Digital Input Disable Register DIDR / #define DIDR _SFR_IO8(0x01) #define AIN1D 1 #define AIN0D 0 / ATtiny USART Baud Rate Register High UBBRH[11:8] / #define UBRRH _SFR_IO8(0x02) / ATtiny USART Control and Status Register C UCSRC / #define UCSRC _SFR_IO8(0x03) #define UMSEL 6 #define UPM1 5 #define UPM0 4 #define USBS 3 #define UCSZ1 2 #define UCSZ0 1 #define UCPOL 0 / 0x04 -> 0x07 Reserved / / ATtiny Analog Comparator Control and Status Register ACSR / #define ACSR _SFR_IO8(0x08) #define ACD 7 #define ACBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 / USART Baud Rate Register Low UBBRL[7:0] / #define UBRRL _SFR_IO8(0x09) / ATtiny USART Control Register UCSRB / #define UCSRB _SFR_IO8(0x0A) #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define UCSZ2 2 #define RXB8 1 #define TXB8 0 / ATtiny USART Status Register UCSRA / #define UCSRA _SFR_IO8(0x0B) #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 #define UPE 2 #define U2X 1 #define MPCM 0 / USART I/O Data Register UBR or RXB[7:0], TXB[7:0] / #define UDR _SFR_IO8(0x0C) #define RXB _SFR_IO8(0x0C) #define TXB _SFR_IO8(0x0C) / ATtiny USI Control Register USICR / #define USICR _SFR_IO8(0x0D) #define USISIE 7 #define USIOIE 6 #define USIWM1 5 #define USIWM0 4 #define USICS1 3 #define USICS0 2 #define USICLK 1 #define USITC 0 / ATtiny USI Status Register USISR / #define USISR _SFR_IO8(0x0E) #define USISIF 7 #define USIOIF 6 #define USIPF 5 #define USIDC 4 #define USICNT3 3 #define USICNT2 2 #define USICNT1 1 #define USICNT0 0 / ATtiny USI Data Register USIDR[7:0] / #define USIDR _SFR_IO8(0x0F) / Input Pins, Port D PIND[6:0] / #define PIND _SFR_IO8(0x10) #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 / Data Direction Register, Port D DDRD[6:0] / #define DDRD _SFR_IO8(0x11) #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 / Data Register, Port D PORTD[6:0] / #define PORTD _SFR_IO8(0x12) #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 / ATtiny General Purpose I/O Register Zero GPIOR0[7:0] / #define GPIOR0 _SFR_IO8(0x13) / ATtiny General Purpose I/O Register One GPIOR1[7:0] / #define GPIOR1 _SFR_IO8(0x14) / ATtiny General Purpose I/O Register Two One GPIOR2[7:0] / #define GPIOR2 _SFR_IO8(0x15) / Input Pins, Port B PORTB[7:0] / #define PINB _SFR_IO8(0x16) #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 / Data Direction Register, Port B PORTB[7:0] / #define DDRB _SFR_IO8(0x17) #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 / Data Register, Port B PORTB[7:0] / #define PORTB _SFR_IO8(0x18) #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 / Port A Input Pins Address PINA[2:0] / #define PINA _SFR_IO8(0x19) #define PINA2 2 #define PINA1 1 #define PINA0 0 / Port A Data Direction Register DDRA[2:0] / #define DDRA _SFR_IO8(0x1A) #define DDRA2 2 #define DDRA1 1 #define DDRA0 0 / Port A Data Register PORTA[2:0] / #define PORTA _SFR_IO8(0x1B) #define PA2 2 #define PA1 1 #define PA0 0 / ATtiny EEPROM Control Register EECR / #define EECR _SFR_IO8(0x1C) #define EEPM1 5 #define EEPM0 4 #define EERIE 3 #define EEMPE 2 #define EEPE 1 #define EERE 0 / EEPROM Data Register / #define EEDR _SFR_IO8(0x1D) / The EEPROM Address Register EEAR[6:0] / #define EEAR _SFR_IO8(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEAR6 6 #define EEAR5 5 #define EEAR4 4 #define EEAR3 3 #define EEAR2 2 #define EEAR1 1 #define EEAR0 0 / 0x1F Reserved / / ATtiny Pin Change Mask Register PCMSK PCINT[7:0] / #define PCMSK _SFR_IO8(0x20) #define PCINT7 7 #define PCINT6 6 #define PCINT5 5 #define PCINT4 4 #define PCINT3 3 #define PCINT2 2 #define PCINT1 1 #define PCINT0 0 / ATtiny Watchdog Timer Control Register WDTCSR / #define WDTCSR _SFR_IO8(0x21) #define WDIF 7 #define WDIE 6 #define WDP3 5 #define WDCE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 / ATtiny Timer/Counter1 Control Register C TCCR1C / #define TCCR1C _SFR_IO8(0x22) #define FOC1A 7 #define FOC1B 6 / General Timer/Counter Control Register GTCCR / #define GTCCR _SFR_IO8(0x23) #define PSR10 0 / T/C 1 Input Capture Register ICR1[15:0] / #define ICR1 _SFR_IO16(0x24) #define ICR1L _SFR_IO8(0x24) #define ICR1H _SFR_IO8(0x25) / ATtiny Clock Prescale Register / #define CLKPR _SFR_IO8(0x26) #define CLKPCE 7 #define CLKPS3 3 #define CLKPS2 2 #define CLKPS1 1 #define CLKPS0 0 / 0x27 Reserved / / ATtiny Output Compare Register 1 B OCR1B[15:0] / #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) / Output Compare Register 1 OCR1A[15:0] / #define OCR1 _SFR_IO16(0x2A) #define OCR1L _SFR_IO8(0x2A) #define OCR1H _SFR_IO8(0x2B) #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) / Timer/Counter 1 TCNT1[15:0] / #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) / ATtiny Timer/Counter 1 Control and Status Register TCCR1B / #define TCCR1B _SFR_IO8(0x2E) #define ICNC1 7 #define ICES1 6 #define WGM13 4 #define WGM12 3 / Was CTC1 in AT90S2313 / #define CS12 2 #define CS11 1 #define CS10 0 / ATtiny Timer/Counter 1 Control Register TCCR1A / #define TCCR1A _SFR_IO8(0x2F) #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define WGM11 1 / Was PWM11 in AT90S2313 / #define WGM10 0 / Was PWM10 in AT90S2313 / / ATtiny Timer/Counter Control Register A TCCR0A / #define TCCR0A _SFR_IO8(0x30) #define COM0A1 7 #define COM0A0 6 #define COM0B1 5 #define COM0B0 4 #define WGM01 1 #define WGM00 0 / ATtiny Oscillator Calibration Register OSCCAL[6:0] / #define OSCCAL _SFR_IO8(0x31) #define CAL6 6 #define CAL5 5 #define CAL4 4 #define CAL3 3 #define CAL2 2 #define CAL1 1 #define CAL0 0 / Timer/Counter 0 TCNT0[7:0] / #define TCNT0 _SFR_IO8(0x32) / ATtiny Timer/Counter 0 Control Register TCCR0B / #define TCCR0B _SFR_IO8(0x33) #define FOC0A 7 #define FOC0B 6 #define WGM02 3 #define CS02 2 #define CS01 1 #define CS00 0 / ATtiny MCU Status Register MCUSR / #define MCUSR _SFR_IO8(0x34) #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 / ATtiny MCU general Control Register MCUCR / #define MCUCR _SFR_IO8(0x35) #define PUD 7 #define SM1 6 #define SE 5 #define SM0 4 / Some preliminary ATtiny2313 data sheets incorrectly refer to this bit as SMD; was SM in AT90S2313. / #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 / ATtiny Output Compare Register A OCR0A[7:0] / #define OCR0A _SFR_IO8(0x36) / ATtiny Store Program Memory Control and Status Register SPMCSR / #define SPMCSR _SFR_IO8(0x37) #define CTPB 4 #define RFLB 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 / The name is used in ATtiny2313.xml file. / #define SELFPRGEN 0 / The name is used in datasheet. / #define SELFPRGE 0 / The name is left for compatibility. / / ATtiny Timer/Counter Interrupt Flag register TIFR / #define TIFR _SFR_IO8(0x38) #define TOV1 7 #define OCF1A 6 #define OCF1B 5 #define ICF1 3 #define OCF0B 2 #define TOV0 1 #define OCF0A 0 / ATtiny Timer/Counter Interrupt MaSK register TIMSK / #define TIMSK _SFR_IO8(0x39) #define TOIE1 7 #define OCIE1A 6 #define OCIE1B 5 #define ICIE1 3 #define OCIE0B 2 #define TOIE0 1 #define OCIE0A 0 / ATtiny External Interrupt Flag Register EIFR, was GIFR / #define EIFR _SFR_IO8(0x3A) #define INTF1 7 #define INTF0 6 #define PCIF 5 / ATtiny General Interrupt MaSK register GIMSK / #define GIMSK _SFR_IO8(0x3B) #define INT1 7 #define INT0 6 #define PCIE 5 / ATtiny Output Compare Register B OCR0B[7:0] / #define OCR0B _SFR_IO8(0x3C) / Interrupt vectors: / / External Interrupt Request 0 / #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) #define SIG_INT0 _VECTOR(1) / External Interrupt Request 1 / #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) #define SIG_INT1 _VECTOR(2) / Timer/Counter1 Capture Event / #define TIMER1_CAPT_vect _VECTOR(3) #define SIG_INPUT_CAPTURE1 _VECTOR(3) #define SIG_TIMER1_CAPT _VECTOR(3) / Timer/Counter1 Compare Match A / #define TIMER1_COMPA_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE1A _VECTOR(4) #define SIG_TIMER1_COMPA _VECTOR(4) / Timer/Counter1 Overflow / #define TIMER1_OVF_vect _VECTOR(5) #define SIG_OVERFLOW1 _VECTOR(5) #define SIG_TIMER1_OVF _VECTOR(5) / Timer/Counter0 Overflow / #define TIMER0_OVF_vect _VECTOR(6) #define SIG_OVERFLOW0 _VECTOR(6) #define SIG_TIMER0_OVF _VECTOR(6) / USART, Rx Complete / #define USART_RX_vect _VECTOR(7) #define SIG_USART0_RECV _VECTOR(7) #define SIG_USART0_RX _VECTOR(7) / USART Data Register Empty / #define USART_UDRE_vect _VECTOR(8) #define SIG_USART0_DATA _VECTOR(8) #define SIG_USART0_UDRE _VECTOR(8) / USART, Tx Complete / #define USART_TX_vect _VECTOR(9) #define SIG_USART0_TRANS _VECTOR(9) #define SIG_USART0_TX _VECTOR(9) / Analog Comparator / #define ANA_COMP_vect _VECTOR(10) #define SIG_COMPARATOR _VECTOR(10) #define SIG_ANALOG_COMP _VECTOR(10) #define PCINT_vect _VECTOR(11) #define SIG_PIN_CHANGE _VECTOR(11) #define SIG_PCINT _VECTOR(11) #define TIMER1_COMPB_vect _VECTOR(12) #define SIG_OUTPUT_COMPARE1B _VECTOR(12) #define SIG_TIMER1_COMPB _VECTOR(12) #define TIMER0_COMPA_vect _VECTOR(13) #define SIG_OUTPUT_COMPARE0A _VECTOR(13) #define SIG_TIMER0_COMPA _VECTOR(13) #define TIMER0_COMPB_vect _VECTOR(14) #define SIG_OUTPUT_COMPARE0B _VECTOR(14) #define SIG_TIMER0_COMPB _VECTOR(14) / USI Start Condition / #define USI_START_vect _VECTOR(15) #define SIG_USI_START _VECTOR(15) #define SIG_USI_START _VECTOR(15) / USI Overflow / #define USI_OVERFLOW_vect _VECTOR(16) #define SIG_USI_OVERFLOW _VECTOR(16) #define SIG_USI_OVERFLOW _VECTOR(16) #define EEPROM_READY_vect _VECTOR(17) #define SIG_EEPROM_READY _VECTOR(17) #define SIG_EE_READY _VECTOR(17) / Watchdog Timer Overflow / #define WDT_OVERFLOW_vect _VECTOR(18) #define SIG_WATCHDOG_TIMEOUT _VECTOR(18) #define SIG_WDT_OVERFLOW _VECTOR(18) / 38 = (182)+2: Number of vectors times two, plus the reset vector / #define _VECTORS_SIZE 38 /* Constants / #define SPM_PAGESIZE 32 #define RAMEND 0xDF #define XRAMEND RAMEND #define E2END 0x7F #define E2PAGESIZE 4 #define FLASHEND 0x07FF / Fuses / #define FUSE_MEMORY_SIZE 3 / Low Fuse Byte / #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL1 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) / High Fuse Byte / #define FUSE_RSTDISBL (unsigned char)~_BV(0) #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) #define FUSE_BODLEVEL2 (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_EESAVE (unsigned char)~_BV(6) #define FUSE_DWEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_SPIEN) / Extended Fuse Byte / #define FUSE_SELFPRGEN (unsigned char)~_BV(0) #define EFUSE_DEFAULT (0xFF) / Lock Bits / #define __LOCK_BITS_EXIST / Signature / #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x91 #define SIGNATURE_2 0x0A #endif / _AVR_IOTN2313_H_ */

ATmega8

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[m8def.inc] [iom8.h]

;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** ;***** Created: 2009-11-03 14:40 ******* Source: ATmega8.xml ************* ;************************************************************************* ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y ;* ;* Number : AVR000 ;* File Name : "m8def.inc" ;* Title : Register/Bit Definitions for the ATmega8 ;* Date : 2009-11-03 ;* Version : 2.35 ;* Support E-mail : avr@atmel.com ;* Target MCU : ATmega8 ;* ;* DESCRIPTION ;* When including this file in the assembly program file, all I/O register ;* names and I/O register bit names appearing in the data book can be used. ;* In addition, the six registers forming the three data pointers X, Y and ;* Z have been assigned names XL - ZH. Highest RAM address for Internal ;* SRAM is also defined ;* ;* The Register names are represented by their hexadecimal address. ;* ;* The Register Bit names are represented by their bit number (0-7). ;* ;* Please observe the difference in using the bit names with instructions ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" ;* (skip if bit in register set/cleared). The following example illustrates ;* this: ;* ;* in r16,PORTB ;read PORTB latch ;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) ;* out PORTB,r16 ;output to PORTB ;* ;* in r16,TIFR ;read the Timer Interrupt Flag Register ;* sbrc r16,TOV0 ;test the overflow flag (use bit#) ;* rjmp TOV0_is_set ;jump if set ;* ... ;otherwise do something else ;************************************************************************* #ifndef _M8DEF_INC_ #define _M8DEF_INC_ #pragma partinc 0 ; ***** SPECIFY DEVICE *************************************************** .device ATmega8 #pragma AVRPART ADMIN PART_NAME ATmega8 .equ SIGNATURE_000 = 0x1e .equ SIGNATURE_001 = 0x93 .equ SIGNATURE_002 = 0x07 #pragma AVRPART CORE CORE_VERSION V2E ; ***** I/O REGISTER DEFINITIONS ***************************************** ; NOTE: ; Definitions marked "MEMORY MAPPED"are extended I/O ports ; and cannot be used with IN/OUT instructions .equ SREG = 0x3f .equ SPL = 0x3d .equ SPH = 0x3e .equ GICR = 0x3b .equ GIFR = 0x3a .equ TIMSK = 0x39 .equ TIFR = 0x38 .equ SPMCR = 0x37 .equ TWCR = 0x36 .equ MCUCR = 0x35 .equ MCUCSR = 0x34 .equ TCCR0 = 0x33 .equ TCNT0 = 0x32 .equ OSCCAL = 0x31 .equ SFIOR = 0x30 .equ TCCR1A = 0x2f .equ TCCR1B = 0x2e .equ TCNT1L = 0x2c .equ TCNT1H = 0x2d .equ OCR1AL = 0x2a .equ OCR1AH = 0x2b .equ OCR1BL = 0x28 .equ OCR1BH = 0x29 .equ ICR1L = 0x26 .equ ICR1H = 0x27 .equ TCCR2 = 0x25 .equ TCNT2 = 0x24 .equ OCR2 = 0x23 .equ ASSR = 0x22 .equ WDTCR = 0x21 .equ UBRRH = 0x20 .equ UCSRC = 0x20 .equ EEARL = 0x1e .equ EEARH = 0x1f .equ EEDR = 0x1d .equ EECR = 0x1c .equ PORTB = 0x18 .equ DDRB = 0x17 .equ PINB = 0x16 .equ PORTC = 0x15 .equ DDRC = 0x14 .equ PINC = 0x13 .equ PORTD = 0x12 .equ DDRD = 0x11 .equ PIND = 0x10 .equ SPDR = 0x0f .equ SPSR = 0x0e .equ SPCR = 0x0d .equ UDR = 0x0c .equ UCSRA = 0x0b .equ UCSRB = 0x0a .equ UBRRL = 0x09 .equ ACSR = 0x08 .equ ADMUX = 0x07 .equ ADCSRA = 0x06 .equ ADCL = 0x04 .equ ADCH = 0x05 .equ TWDR = 0x03 .equ TWAR = 0x02 .equ TWSR = 0x01 .equ TWBR = 0x00 ; ***** BIT DEFINITIONS ************************************************** ; ***** ANALOG_COMPARATOR ************ ; SFIOR - Special Function IO Register .equ ACME = 3 ; Analog Comparator Multiplexer Enable ; ACSR - Analog Comparator Control And Status Register .equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 .equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 .equ ACIC = 2 ; Analog Comparator Input Capture Enable .equ ACIE = 3 ; Analog Comparator Interrupt Enable .equ ACI = 4 ; Analog Comparator Interrupt Flag .equ ACO = 5 ; Analog Compare Output .equ ACBG = 6 ; Analog Comparator Bandgap Select .equ ACD = 7 ; Analog Comparator Disable ; ***** SPI ************************** ; SPDR - SPI Data Register .equ SPDR0 = 0 ; SPI Data Register bit 0 .equ SPDR1 = 1 ; SPI Data Register bit 1 .equ SPDR2 = 2 ; SPI Data Register bit 2 .equ SPDR3 = 3 ; SPI Data Register bit 3 .equ SPDR4 = 4 ; SPI Data Register bit 4 .equ SPDR5 = 5 ; SPI Data Register bit 5 .equ SPDR6 = 6 ; SPI Data Register bit 6 .equ SPDR7 = 7 ; SPI Data Register bit 7 ; SPSR - SPI Status Register .equ SPI2X = 0 ; Double SPI Speed Bit .equ WCOL = 6 ; Write Collision Flag .equ SPIF = 7 ; SPI Interrupt Flag ; SPCR - SPI Control Register .equ SPR0 = 0 ; SPI Clock Rate Select 0 .equ SPR1 = 1 ; SPI Clock Rate Select 1 .equ CPHA = 2 ; Clock Phase .equ CPOL = 3 ; Clock polarity .equ MSTR = 4 ; Master/Slave Select .equ DORD = 5 ; Data Order .equ SPE = 6 ; SPI Enable .equ SPIE = 7 ; SPI Interrupt Enable ; ***** EXTERNAL_INTERRUPT *********** ; GICR - General Interrupt Control Register .equ GIMSK = GICR ; For compatibility .equ IVCE = 0 ; Interrupt Vector Change Enable .equ IVSEL = 1 ; Interrupt Vector Select .equ INT0 = 6 ; External Interrupt Request 0 Enable .equ INT1 = 7 ; External Interrupt Request 1 Enable ; GIFR - General Interrupt Flag Register .equ INTF0 = 6 ; External Interrupt Flag 0 .equ INTF1 = 7 ; External Interrupt Flag 1 ; MCUCR - MCU Control Register .equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 .equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 .equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 .equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 ; ***** TIMER_COUNTER_0 ************** ; TIMSK - Timer/Counter Interrupt Mask Register .equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable ; TIFR - Timer/Counter Interrupt Flag register .equ TOV0 = 0 ; Timer/Counter0 Overflow Flag ; TCCR0 - Timer/Counter0 Control Register .equ CS00 = 0 ; Clock Select0 bit 0 .equ CS01 = 1 ; Clock Select0 bit 1 .equ CS02 = 2 ; Clock Select0 bit 2 ; TCNT0 - Timer Counter 0 .equ TCNT00 = 0 ; Timer Counter 0 bit 0 .equ TCNT01 = 1 ; Timer Counter 0 bit 1 .equ TCNT02 = 2 ; Timer Counter 0 bit 2 .equ TCNT03 = 3 ; Timer Counter 0 bit 3 .equ TCNT04 = 4 ; Timer Counter 0 bit 4 .equ TCNT05 = 5 ; Timer Counter 0 bit 5 .equ TCNT06 = 6 ; Timer Counter 0 bit 6 .equ TCNT07 = 7 ; Timer Counter 0 bit 7 ; ***** TIMER_COUNTER_1 ************** ; TIMSK - Timer/Counter Interrupt Mask Register .equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable .equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable .equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable .equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable ; TIFR - Timer/Counter Interrupt Flag register .equ TOV1 = 2 ; Timer/Counter1 Overflow Flag .equ OCF1B = 3 ; Output Compare Flag 1B .equ OCF1A = 4 ; Output Compare Flag 1A .equ ICF1 = 5 ; Input Capture Flag 1 ; TCCR1A - Timer/Counter1 Control Register A .equ WGM10 = 0 ; Waveform Generation Mode .equ PWM10 = WGM10 ; For compatibility .equ WGM11 = 1 ; Waveform Generation Mode .equ PWM11 = WGM11 ; For compatibility .equ FOC1B = 2 ; Force Output Compare 1B .equ FOC1A = 3 ; Force Output Compare 1A .equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 .equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 .equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0 .equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 ; TCCR1B - Timer/Counter1 Control Register B .equ CS10 = 0 ; Prescaler source of Timer/Counter 1 .equ CS11 = 1 ; Prescaler source of Timer/Counter 1 .equ CS12 = 2 ; Prescaler source of Timer/Counter 1 .equ WGM12 = 3 ; Waveform Generation Mode .equ CTC10 = WGM12 ; For compatibility .equ CTC1 = WGM12 ; For compatibility .equ WGM13 = 4 ; Waveform Generation Mode .equ CTC11 = WGM13 ; For compatibility .equ ICES1 = 6 ; Input Capture 1 Edge Select .equ ICNC1 = 7 ; Input Capture 1 Noise Canceler ; ***** TIMER_COUNTER_2 ************** ; TIMSK - Timer/Counter Interrupt Mask register .equ TOIE2 = 6 ; Timer/Counter2 Overflow Interrupt Enable .equ OCIE2 = 7 ; Timer/Counter2 Output Compare Match Interrupt Enable ; TIFR - Timer/Counter Interrupt Flag Register .equ TOV2 = 6 ; Timer/Counter2 Overflow Flag .equ OCF2 = 7 ; Output Compare Flag 2 ; TCCR2 - Timer/Counter2 Control Register .equ CS20 = 0 ; Clock Select bit 0 .equ CS21 = 1 ; Clock Select bit 1 .equ CS22 = 2 ; Clock Select bit 2 .equ WGM21 = 3 ; Waveform Generation Mode .equ CTC2 = WGM21 ; For compatibility .equ COM20 = 4 ; Compare Output Mode bit 0 .equ COM21 = 5 ; Compare Output Mode bit 1 .equ WGM20 = 6 ; Waveform Genration Mode .equ PWM2 = WGM20 ; For compatibility .equ FOC2 = 7 ; Force Output Compare ; TCNT2 - Timer/Counter2 .equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 .equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 .equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 .equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 .equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 .equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 .equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 .equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 ; OCR2 - Timer/Counter2 Output Compare Register .equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 .equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 .equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 .equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 .equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 .equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 .equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 .equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 ; ASSR - Asynchronous Status Register .equ TCR2UB = 0 ; Timer/counter Control Register2 Update Busy .equ OCR2UB = 1 ; Output Compare Register2 Update Busy .equ TCN2UB = 2 ; Timer/Counter2 Update Busy .equ AS2 = 3 ; Asynchronous Timer/counter2 ; SFIOR - Special Function IO Register .equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 ; ***** USART ************************ ; UDR - USART I/O Data Register .equ UDR0 = 0 ; USART I/O Data Register bit 0 .equ UDR1 = 1 ; USART I/O Data Register bit 1 .equ UDR2 = 2 ; USART I/O Data Register bit 2 .equ UDR3 = 3 ; USART I/O Data Register bit 3 .equ UDR4 = 4 ; USART I/O Data Register bit 4 .equ UDR5 = 5 ; USART I/O Data Register bit 5 .equ UDR6 = 6 ; USART I/O Data Register bit 6 .equ UDR7 = 7 ; USART I/O Data Register bit 7 ; UCSRA - USART Control and Status Register A .equ USR = UCSRA ; For compatibility .equ MPCM = 0 ; Multi-processor Communication Mode .equ U2X = 1 ; Double the USART transmission speed .equ UPE = 2 ; Parity Error .equ PE = UPE ; For compatibility .equ DOR = 3 ; Data overRun .equ FE = 4 ; Framing Error .equ UDRE = 5 ; USART Data Register Empty .equ TXC = 6 ; USART Transmitt Complete .equ RXC = 7 ; USART Receive Complete ; UCSRB - USART Control and Status Register B .equ UCR = UCSRB ; For compatibility .equ TXB8 = 0 ; Transmit Data Bit 8 .equ RXB8 = 1 ; Receive Data Bit 8 .equ UCSZ2 = 2 ; Character Size .equ CHR9 = UCSZ2 ; For compatibility .equ TXEN = 3 ; Transmitter Enable .equ RXEN = 4 ; Receiver Enable .equ UDRIE = 5 ; USART Data register Empty Interrupt Enable .equ TXCIE = 6 ; TX Complete Interrupt Enable .equ RXCIE = 7 ; RX Complete Interrupt Enable ; UCSRC - USART Control and Status Register C .equ UCPOL = 0 ; Clock Polarity .equ UCSZ0 = 1 ; Character Size .equ UCSZ1 = 2 ; Character Size .equ USBS = 3 ; Stop Bit Select .equ UPM0 = 4 ; Parity Mode Bit 0 .equ UPM1 = 5 ; Parity Mode Bit 1 .equ UMSEL = 6 ; USART Mode Select .equ URSEL = 7 ; Register Select .equ UBRRHI = UBRRH ; For compatibility ; ***** TWI ************************** ; TWBR - TWI Bit Rate register .equ I2BR = TWBR ; For compatibility .equ TWBR0 = 0 ; .equ TWBR1 = 1 ; .equ TWBR2 = 2 ; .equ TWBR3 = 3 ; .equ TWBR4 = 4 ; .equ TWBR5 = 5 ; .equ TWBR6 = 6 ; .equ TWBR7 = 7 ; ; TWCR - TWI Control Register .equ I2CR = TWCR ; For compatibility .equ TWIE = 0 ; TWI Interrupt Enable .equ I2IE = TWIE ; For compatibility .equ TWEN = 2 ; TWI Enable Bit .equ I2EN = TWEN ; For compatibility .equ ENI2C = TWEN ; For compatibility .equ TWWC = 3 ; TWI Write Collition Flag .equ I2WC = TWWC ; For compatibility .equ TWSTO = 4 ; TWI Stop Condition Bit .equ I2STO = TWSTO ; For compatibility .equ TWSTA = 5 ; TWI Start Condition Bit .equ I2STA = TWSTA ; For compatibility .equ TWEA = 6 ; TWI Enable Acknowledge Bit .equ I2EA = TWEA ; For compatibility .equ TWINT = 7 ; TWI Interrupt Flag .equ I2INT = TWINT ; For compatibility ; TWSR - TWI Status Register .equ I2SR = TWSR ; For compatibility .equ TWPS0 = 0 ; TWI Prescaler .equ TWS0 = TWPS0 ; For compatibility .equ I2GCE = TWPS0 ; For compatibility .equ TWPS1 = 1 ; TWI Prescaler .equ TWS1 = TWPS1 ; For compatibility .equ TWS3 = 3 ; TWI Status .equ I2S3 = TWS3 ; For compatibility .equ TWS4 = 4 ; TWI Status .equ I2S4 = TWS4 ; For compatibility .equ TWS5 = 5 ; TWI Status .equ I2S5 = TWS5 ; For compatibility .equ TWS6 = 6 ; TWI Status .equ I2S6 = TWS6 ; For compatibility .equ TWS7 = 7 ; TWI Status .equ I2S7 = TWS7 ; For compatibility ; TWDR - TWI Data register .equ I2DR = TWDR ; For compatibility .equ TWD0 = 0 ; TWI Data Register Bit 0 .equ TWD1 = 1 ; TWI Data Register Bit 1 .equ TWD2 = 2 ; TWI Data Register Bit 2 .equ TWD3 = 3 ; TWI Data Register Bit 3 .equ TWD4 = 4 ; TWI Data Register Bit 4 .equ TWD5 = 5 ; TWI Data Register Bit 5 .equ TWD6 = 6 ; TWI Data Register Bit 6 .equ TWD7 = 7 ; TWI Data Register Bit 7 ; TWAR - TWI (Slave) Address register .equ I2AR = TWAR ; For compatibility .equ TWGCE = 0 ; TWI General Call Recognition Enable Bit .equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 .equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 .equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 .equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 .equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 .equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 .equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 ; ***** WATCHDOG ********************* ; WDTCR - Watchdog Timer Control Register .equ WDTCSR = WDTCR ; For compatibility .equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 .equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 .equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 .equ WDE = 3 ; Watch Dog Enable .equ WDCE = 4 ; Watchdog Change Enable .equ WDTOE = WDCE ; For compatibility ; ***** PORTB ************************ ; PORTB - Port B Data Register .equ PORTB0 = 0 ; Port B Data Register bit 0 .equ PB0 = 0 ; For compatibility .equ PORTB1 = 1 ; Port B Data Register bit 1 .equ PB1 = 1 ; For compatibility .equ PORTB2 = 2 ; Port B Data Register bit 2 .equ PB2 = 2 ; For compatibility .equ PORTB3 = 3 ; Port B Data Register bit 3 .equ PB3 = 3 ; For compatibility .equ PORTB4 = 4 ; Port B Data Register bit 4 .equ PB4 = 4 ; For compatibility .equ PORTB5 = 5 ; Port B Data Register bit 5 .equ PB5 = 5 ; For compatibility .equ PORTB6 = 6 ; Port B Data Register bit 6 .equ PB6 = 6 ; For compatibility .equ PORTB7 = 7 ; Port B Data Register bit 7 .equ PB7 = 7 ; For compatibility ; DDRB - Port B Data Direction Register .equ DDB0 = 0 ; Port B Data Direction Register bit 0 .equ DDB1 = 1 ; Port B Data Direction Register bit 1 .equ DDB2 = 2 ; Port B Data Direction Register bit 2 .equ DDB3 = 3 ; Port B Data Direction Register bit 3 .equ DDB4 = 4 ; Port B Data Direction Register bit 4 .equ DDB5 = 5 ; Port B Data Direction Register bit 5 .equ DDB6 = 6 ; Port B Data Direction Register bit 6 .equ DDB7 = 7 ; Port B Data Direction Register bit 7 ; PINB - Port B Input Pins .equ PINB0 = 0 ; Port B Input Pins bit 0 .equ PINB1 = 1 ; Port B Input Pins bit 1 .equ PINB2 = 2 ; Port B Input Pins bit 2 .equ PINB3 = 3 ; Port B Input Pins bit 3 .equ PINB4 = 4 ; Port B Input Pins bit 4 .equ PINB5 = 5 ; Port B Input Pins bit 5 .equ PINB6 = 6 ; Port B Input Pins bit 6 .equ PINB7 = 7 ; Port B Input Pins bit 7 ; ***** PORTC ************************ ; PORTC - Port C Data Register .equ PORTC0 = 0 ; Port C Data Register bit 0 .equ PC0 = 0 ; For compatibility .equ PORTC1 = 1 ; Port C Data Register bit 1 .equ PC1 = 1 ; For compatibility .equ PORTC2 = 2 ; Port C Data Register bit 2 .equ PC2 = 2 ; For compatibility .equ PORTC3 = 3 ; Port C Data Register bit 3 .equ PC3 = 3 ; For compatibility .equ PORTC4 = 4 ; Port C Data Register bit 4 .equ PC4 = 4 ; For compatibility .equ PORTC5 = 5 ; Port C Data Register bit 5 .equ PC5 = 5 ; For compatibility .equ PORTC6 = 6 ; Port C Data Register bit 6 .equ PC6 = 6 ; For compatibility ; DDRC - Port C Data Direction Register .equ DDC0 = 0 ; Port C Data Direction Register bit 0 .equ DDC1 = 1 ; Port C Data Direction Register bit 1 .equ DDC2 = 2 ; Port C Data Direction Register bit 2 .equ DDC3 = 3 ; Port C Data Direction Register bit 3 .equ DDC4 = 4 ; Port C Data Direction Register bit 4 .equ DDC5 = 5 ; Port C Data Direction Register bit 5 .equ DDC6 = 6 ; Port C Data Direction Register bit 6 ; PINC - Port C Input Pins .equ PINC0 = 0 ; Port C Input Pins bit 0 .equ PINC1 = 1 ; Port C Input Pins bit 1 .equ PINC2 = 2 ; Port C Input Pins bit 2 .equ PINC3 = 3 ; Port C Input Pins bit 3 .equ PINC4 = 4 ; Port C Input Pins bit 4 .equ PINC5 = 5 ; Port C Input Pins bit 5 .equ PINC6 = 6 ; Port C Input Pins bit 6 ; ***** PORTD ************************ ; PORTD - Port D Data Register .equ PORTD0 = 0 ; Port D Data Register bit 0 .equ PD0 = 0 ; For compatibility .equ PORTD1 = 1 ; Port D Data Register bit 1 .equ PD1 = 1 ; For compatibility .equ PORTD2 = 2 ; Port D Data Register bit 2 .equ PD2 = 2 ; For compatibility .equ PORTD3 = 3 ; Port D Data Register bit 3 .equ PD3 = 3 ; For compatibility .equ PORTD4 = 4 ; Port D Data Register bit 4 .equ PD4 = 4 ; For compatibility .equ PORTD5 = 5 ; Port D Data Register bit 5 .equ PD5 = 5 ; For compatibility .equ PORTD6 = 6 ; Port D Data Register bit 6 .equ PD6 = 6 ; For compatibility .equ PORTD7 = 7 ; Port D Data Register bit 7 .equ PD7 = 7 ; For compatibility ; DDRD - Port D Data Direction Register .equ DDD0 = 0 ; Port D Data Direction Register bit 0 .equ DDD1 = 1 ; Port D Data Direction Register bit 1 .equ DDD2 = 2 ; Port D Data Direction Register bit 2 .equ DDD3 = 3 ; Port D Data Direction Register bit 3 .equ DDD4 = 4 ; Port D Data Direction Register bit 4 .equ DDD5 = 5 ; Port D Data Direction Register bit 5 .equ DDD6 = 6 ; Port D Data Direction Register bit 6 .equ DDD7 = 7 ; Port D Data Direction Register bit 7 ; PIND - Port D Input Pins .equ PIND0 = 0 ; Port D Input Pins bit 0 .equ PIND1 = 1 ; Port D Input Pins bit 1 .equ PIND2 = 2 ; Port D Input Pins bit 2 .equ PIND3 = 3 ; Port D Input Pins bit 3 .equ PIND4 = 4 ; Port D Input Pins bit 4 .equ PIND5 = 5 ; Port D Input Pins bit 5 .equ PIND6 = 6 ; Port D Input Pins bit 6 .equ PIND7 = 7 ; Port D Input Pins bit 7 ; ***** EEPROM *********************** ; EEDR - EEPROM Data Register .equ EEDR0 = 0 ; EEPROM Data Register bit 0 .equ EEDR1 = 1 ; EEPROM Data Register bit 1 .equ EEDR2 = 2 ; EEPROM Data Register bit 2 .equ EEDR3 = 3 ; EEPROM Data Register bit 3 .equ EEDR4 = 4 ; EEPROM Data Register bit 4 .equ EEDR5 = 5 ; EEPROM Data Register bit 5 .equ EEDR6 = 6 ; EEPROM Data Register bit 6 .equ EEDR7 = 7 ; EEPROM Data Register bit 7 ; EECR - EEPROM Control Register .equ EERE = 0 ; EEPROM Read Enable .equ EEWE = 1 ; EEPROM Write Enable .equ EEMWE = 2 ; EEPROM Master Write Enable .equ EEWEE = EEMWE ; For compatibility .equ EERIE = 3 ; EEPROM Ready Interrupt Enable ; ***** CPU ************************** ; SREG - Status Register .equ SREG_C = 0 ; Carry Flag .equ SREG_Z = 1 ; Zero Flag .equ SREG_N = 2 ; Negative Flag .equ SREG_V = 3 ; Two's Complement Overflow Flag .equ SREG_S = 4 ; Sign Bit .equ SREG_H = 5 ; Half Carry Flag .equ SREG_T = 6 ; Bit Copy Storage .equ SREG_I = 7 ; Global Interrupt Enable ; MCUCR - MCU Control Register ;.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 ;.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 ;.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 ;.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 .equ SM0 = 4 ; Sleep Mode Select .equ SM1 = 5 ; Sleep Mode Select .equ SM2 = 6 ; Sleep Mode Select .equ SE = 7 ; Sleep Enable ; MCUCSR - MCU Control And Status Register .equ MCUSR = MCUCSR ; For compatibility .equ PORF = 0 ; Power-on reset flag .equ EXTRF = 1 ; External Reset Flag .equ BORF = 2 ; Brown-out Reset Flag .equ WDRF = 3 ; Watchdog Reset Flag ; OSCCAL - Oscillator Calibration Value .equ CAL0 = 0 ; Oscillator Calibration Value Bit0 .equ CAL1 = 1 ; Oscillator Calibration Value Bit1 .equ CAL2 = 2 ; Oscillator Calibration Value Bit2 .equ CAL3 = 3 ; Oscillator Calibration Value Bit3 .equ CAL4 = 4 ; Oscillator Calibration Value Bit4 .equ CAL5 = 5 ; Oscillator Calibration Value Bit5 .equ CAL6 = 6 ; Oscillator Calibration Value Bit6 .equ CAL7 = 7 ; Oscillator Calibration Value Bit7 ; SPMCR - Store Program Memory Control Register .equ SPMEN = 0 ; Store Program Memory Enable .equ PGERS = 1 ; Page Erase .equ PGWRT = 2 ; Page Write .equ BLBSET = 3 ; Boot Lock Bit Set .equ RWWSRE = 4 ; Read-While-Write Section Read Enable .equ RWWSB = 6 ; Read-While-Write Section Busy .equ SPMIE = 7 ; SPM Interrupt Enable ; SFIOR - Special Function IO Register .equ PSR10 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 .equ PUD = 2 ; Pull-up Disable .equ ADHSM = 4 ; ADC High Speed Mode ; ***** AD_CONVERTER ***************** ; ADMUX - The ADC multiplexer Selection Register .equ MUX0 = 0 ; Analog Channel and Gain Selection Bits .equ MUX1 = 1 ; Analog Channel and Gain Selection Bits .equ MUX2 = 2 ; Analog Channel and Gain Selection Bits .equ MUX3 = 3 ; Analog Channel and Gain Selection Bits .equ ADLAR = 5 ; Left Adjust Result .equ REFS0 = 6 ; Reference Selection Bit 0 .equ REFS1 = 7 ; Reference Selection Bit 1 ; ADCSRA - The ADC Control and Status register .equ ADCSR = ADCSRA ; For compatibility .equ ADPS0 = 0 ; ADC Prescaler Select Bits .equ ADPS1 = 1 ; ADC Prescaler Select Bits .equ ADPS2 = 2 ; ADC Prescaler Select Bits .equ ADIE = 3 ; ADC Interrupt Enable .equ ADIF = 4 ; ADC Interrupt Flag .equ ADFR = 5 ; ADC Free Running Select .equ ADSC = 6 ; ADC Start Conversion .equ ADEN = 7 ; ADC Enable ; ***** LOCKSBITS ******************************************************** .equ LB1 = 0 ; Lock bit .equ LB2 = 1 ; Lock bit .equ BLB01 = 2 ; Boot Lock bit .equ BLB02 = 3 ; Boot Lock bit .equ BLB11 = 4 ; Boot lock bit .equ BLB12 = 5 ; Boot lock bit ; ***** FUSES ************************************************************ ; LOW fuse bits .equ CKSEL0 = 0 ; Select Clock Source .equ CKSEL1 = 1 ; Select Clock Source .equ CKSEL2 = 2 ; Select Clock Source .equ CKSEL3 = 3 ; Select Clock Source .equ SUT0 = 4 ; Select start-up time .equ SUT1 = 5 ; Select start-up time .equ BODEN = 6 ; Brown out detector enable .equ BODLEVEL = 7 ; Brown out detector trigger level ; HIGH fuse bits .equ BOOTRST = 0 ; Select Reset Vector .equ BOOTSZ0 = 1 ; Select Boot Size .equ BOOTSZ1 = 2 ; Select Boot Size .equ EESAVE = 3 ; EEPROM memory is preserved through chip erase .equ CKOPT = 4 ; Oscillator Options .equ SPIEN = 5 ; Enable Serial programming and Data Downloading .equ WTDON = 6 ; Enable watchdog .equ RSTDISBL = 7 ; Disable reset ; ***** CPU REGISTER DEFINITIONS ***************************************** .def XH = r27 .def XL = r26 .def YH = r29 .def YL = r28 .def ZH = r31 .def ZL = r30 ; ***** DATA MEMORY DECLARATIONS ***************************************** .equ FLASHEND = 0x0fff ; Note: Word address .equ IOEND = 0x003f .equ SRAM_START = 0x0060 .equ SRAM_SIZE = 1024 .equ RAMEND = 0x045f .equ XRAMEND = 0x0000 .equ E2END = 0x01ff .equ EEPROMEND = 0x01ff .equ EEADRBITS = 9 #pragma AVRPART MEMORY PROG_FLASH 8192 #pragma AVRPART MEMORY EEPROM 512 #pragma AVRPART MEMORY INT_SRAM SIZE 1024 #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 ; ***** BOOTLOADER DECLARATIONS ****************************************** .equ NRWW_START_ADDR = 0xc00 .equ NRWW_STOP_ADDR = 0xfff .equ RWW_START_ADDR = 0x0 .equ RWW_STOP_ADDR = 0xbff .equ PAGESIZE = 32 .equ FIRSTBOOTSTART = 0xf80 .equ SECONDBOOTSTART = 0xf00 .equ THIRDBOOTSTART = 0xe00 .equ FOURTHBOOTSTART = 0xc00 .equ SMALLBOOTSTART = FIRSTBOOTSTART .equ LARGEBOOTSTART = FOURTHBOOTSTART ; ***** INTERRUPT VECTORS ************************************************ .equ INT0addr = 0x0001 ; External Interrupt Request 0 .equ INT1addr = 0x0002 ; External Interrupt Request 1 .equ OC2addr = 0x0003 ; Timer/Counter2 Compare Match .equ OVF2addr = 0x0004 ; Timer/Counter2 Overflow .equ ICP1addr = 0x0005 ; Timer/Counter1 Capture Event .equ OC1Aaddr = 0x0006 ; Timer/Counter1 Compare Match A .equ OC1Baddr = 0x0007 ; Timer/Counter1 Compare Match B .equ OVF1addr = 0x0008 ; Timer/Counter1 Overflow .equ OVF0addr = 0x0009 ; Timer/Counter0 Overflow .equ SPIaddr = 0x000a ; Serial Transfer Complete .equ URXCaddr = 0x000b ; USART, Rx Complete .equ UDREaddr = 0x000c ; USART Data Register Empty .equ UTXCaddr = 0x000d ; USART, Tx Complete .equ ADCCaddr = 0x000e ; ADC Conversion Complete .equ ERDYaddr = 0x000f ; EEPROM Ready .equ ACIaddr = 0x0010 ; Analog Comparator .equ TWIaddr = 0x0011 ; 2-wire Serial Interface .equ SPMRaddr = 0x0012 ; Store Program Memory Ready .equ INT_VECTORS_SIZE = 19 ; size in words #pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break #endif /* _M8DEF_INC_ */ ; ***** END OF FILE ****************************************************** /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom8.h,v 1.14.2.7 2009/02/11 18:05:30 arcanum Exp $ */ /* avr/iom8.h - definitions for ATmega8 */ #ifndef _AVR_IOM8_H_ #define _AVR_IOM8_H_ 1 /* This file should only be included from <avr/io.h>, never directly. */ #ifndef _AVR_IO_H_ # error "Include <avr/io.h> instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom8.h" #else # error "Attempt to include more than one <avr/ioXXX.h> file." #endif /* I/O registers */ /* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ #define TWBR _SFR_IO8(0x00) #define TWSR _SFR_IO8(0x01) #define TWAR _SFR_IO8(0x02) #define TWDR _SFR_IO8(0x03) /* ADC */ #define ADCW _SFR_IO16(0x04) #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) #define ADCSR _SFR_IO8(0x06) #define ADCSRA _SFR_IO8(0x06) /* Changed in 2486H-AVR-09/02 */ #define ADMUX _SFR_IO8(0x07) /* analog comparator */ #define ACSR _SFR_IO8(0x08) /* USART */ #define UBRRL _SFR_IO8(0x09) #define UCSRB _SFR_IO8(0x0A) #define UCSRA _SFR_IO8(0x0B) #define UDR _SFR_IO8(0x0C) /* SPI */ #define SPCR _SFR_IO8(0x0D) #define SPSR _SFR_IO8(0x0E) #define SPDR _SFR_IO8(0x0F) /* Port D */ #define PIND _SFR_IO8(0x10) #define DDRD _SFR_IO8(0x11) #define PORTD _SFR_IO8(0x12) /* Port C */ #define PINC _SFR_IO8(0x13) #define DDRC _SFR_IO8(0x14) #define PORTC _SFR_IO8(0x15) /* Port B */ #define PINB _SFR_IO8(0x16) #define DDRB _SFR_IO8(0x17) #define PORTB _SFR_IO8(0x18) /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEARH _SFR_IO8(0x1F) #define UCSRC _SFR_IO8(0x20) #define UBRRH _SFR_IO8(0x20) #define WDTCR _SFR_IO8(0x21) #define ASSR _SFR_IO8(0x22) /* Timer 2 */ #define OCR2 _SFR_IO8(0x23) #define TCNT2 _SFR_IO8(0x24) #define TCCR2 _SFR_IO8(0x25) /* Timer 1 */ #define ICR1 _SFR_IO16(0x26) #define ICR1L _SFR_IO8(0x26) #define ICR1H _SFR_IO8(0x27) #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) #define TCCR1B _SFR_IO8(0x2E) #define TCCR1A _SFR_IO8(0x2F) #define SFIOR _SFR_IO8(0x30) #define OSCCAL _SFR_IO8(0x31) /* Timer 0 */ #define TCNT0 _SFR_IO8(0x32) #define TCCR0 _SFR_IO8(0x33) #define MCUCSR _SFR_IO8(0x34) #define MCUSR _SFR_IO8(0x34) /* Defined as an alias for MCUCSR. */ #define MCUCR _SFR_IO8(0x35) #define TWCR _SFR_IO8(0x36) #define SPMCR _SFR_IO8(0x37) #define TIFR _SFR_IO8(0x38) #define TIMSK _SFR_IO8(0x39) #define GIFR _SFR_IO8(0x3A) #define GIMSK _SFR_IO8(0x3B) #define GICR _SFR_IO8(0x3B) /* Changed in 2486H-AVR-09/02 */ /* 0x3C reserved (OCR0?) */ /* 0x3D..0x3E SP */ /* 0x3F SREG */ /* Interrupt vectors */ /* External Interrupt Request 0 */ #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt Request 1 */ #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect _VECTOR(3) #define SIG_OUTPUT_COMPARE2 _VECTOR(3) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect _VECTOR(4) #define SIG_OVERFLOW2 _VECTOR(4) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect _VECTOR(5) #define SIG_INPUT_CAPTURE1 _VECTOR(5) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect _VECTOR(6) #define SIG_OUTPUT_COMPARE1A _VECTOR(6) /* Timer/Counter1 Compare Match B */ #define TIMER1_COMPB_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1B _VECTOR(7) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect _VECTOR(8) #define SIG_OVERFLOW1 _VECTOR(8) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect _VECTOR(9) #define SIG_OVERFLOW0 _VECTOR(9) /* Serial Transfer Complete */ #define SPI_STC_vect _VECTOR(10) #define SIG_SPI _VECTOR(10) /* USART, Rx Complete */ #define USART_RXC_vect _VECTOR(11) #define SIG_UART_RECV _VECTOR(11) /* USART Data Register Empty */ #define USART_UDRE_vect _VECTOR(12) #define SIG_UART_DATA _VECTOR(12) /* USART, Tx Complete */ #define USART_TXC_vect _VECTOR(13) #define SIG_UART_TRANS _VECTOR(13) /* ADC Conversion Complete */ #define ADC_vect _VECTOR(14) #define SIG_ADC _VECTOR(14) /* EEPROM Ready */ #define EE_RDY_vect _VECTOR(15) #define SIG_EEPROM_READY _VECTOR(15) /* Analog Comparator */ #define ANA_COMP_vect _VECTOR(16) #define SIG_COMPARATOR _VECTOR(16) /* 2-wire Serial Interface */ #define TWI_vect _VECTOR(17) #define SIG_2WIRE_SERIAL _VECTOR(17) /* Store Program Memory Ready */ #define SPM_RDY_vect _VECTOR(18) #define SIG_SPM_READY _VECTOR(18) #define _VECTORS_SIZE 38 /* Bit numbers */ /* GIMSK / GICR */ #define INT1 7 #define INT0 6 #define IVSEL 1 #define IVCE 0 /* GIFR */ #define INTF1 7 #define INTF0 6 /* TIMSK */ #define OCIE2 7 #define TOIE2 6 #define TICIE1 5 #define OCIE1A 4 #define OCIE1B 3 #define TOIE1 2 /* bit 1 reserved (OCIE0?) */ #define TOIE0 0 /* TIFR */ #define OCF2 7 #define TOV2 6 #define ICF1 5 #define OCF1A 4 #define OCF1B 3 #define TOV1 2 /* bit 1 reserved (OCF0?) */ #define TOV0 0 /* SPMCR */ #define SPMIE 7 #define RWWSB 6 /* bit 5 reserved */ #define RWWSRE 4 #define BLBSET 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 /* TWCR */ #define TWINT 7 #define TWEA 6 #define TWSTA 5 #define TWSTO 4 #define TWWC 3 #define TWEN 2 /* bit 1 reserved (TWI_TST?) */ #define TWIE 0 /* TWAR */ #define TWA6 7 #define TWA5 6 #define TWA4 5 #define TWA3 4 #define TWA2 3 #define TWA1 2 #define TWA0 1 #define TWGCE 0 /* TWSR */ #define TWS7 7 #define TWS6 6 #define TWS5 5 #define TWS4 4 #define TWS3 3 /* bit 2 reserved */ #define TWPS1 1 #define TWPS0 0 /* MCUCR */ #define SE 7 #define SM2 6 #define SM1 5 #define SM0 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* MCUCSR */ /* bits 7-4 reserved */ #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 /* The ADHSM bit has been removed from all documentation, as being not needed at all since the comparator has proven to be fast enough even without feeding it more power. */ /* SFIOR */ /* bits 7-5 reserved */ #define ACME 3 #define PUD 2 #define PSR2 1 #define PSR10 0 /* TCCR0 */ /* bits 7-3 reserved */ #define CS02 2 #define CS01 1 #define CS00 0 /* TCCR2 */ #define FOC2 7 #define WGM20 6 #define COM21 5 #define COM20 4 #define WGM21 3 #define CS22 2 #define CS21 1 #define CS20 0 /* ASSR */ /* bits 7-4 reserved */ #define AS2 3 #define TCN2UB 2 #define OCR2UB 1 #define TCR2UB 0 /* TCCR1A */ #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define FOC1A 3 #define FOC1B 2 #define WGM11 1 #define WGM10 0 /* TCCR1B */ #define ICNC1 7 #define ICES1 6 /* bit 5 reserved */ #define WGM13 4 #define WGM12 3 #define CS12 2 #define CS11 1 #define CS10 0 /* WDTCR */ /* bits 7-5 reserved */ #define WDCE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* UBRRH */ #define URSEL 7 /* UCSRC */ #define URSEL 7 #define UMSEL 6 #define UPM1 5 #define UPM0 4 #define USBS 3 #define UCSZ1 2 #define UCSZ0 1 #define UCPOL 0 /* PORTB */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* DDRB */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* PINB */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* PORTC */ #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* DDRC */ #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 /* PINC */ #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 /* PORTD */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* DDRD */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* PIND */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* SPSR */ #define SPIF 7 #define WCOL 6 #define SPI2X 0 /* SPCR */ #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 /* UCSRA */ #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 #define PE 2 #define U2X 1 #define MPCM 0 /* UCSRB */ #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define UCSZ2 2 #define RXB8 1 #define TXB8 0 /* ACSR */ #define ACD 7 #define ACBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 /* ADCSR / ADCSRA */ #define ADEN 7 #define ADSC 6 #define ADFR 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 /* ADMUX */ #define REFS1 7 #define REFS0 6 #define ADLAR 5 /* bit 4 reserved */ #define MUX3 3 #define MUX2 2 #define MUX1 1 #define MUX0 0 /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* Constants */ #define SPM_PAGESIZE 64 #define RAMEND 0x45F #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x1FFF /* Fuses */ #define FUSE_MEMORY_SIZE 2 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_BODEN (unsigned char)~_BV(6) #define FUSE_BODLEVEL (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_CKOPT (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_WDTON (unsigned char)~_BV(6) #define FUSE_RSTDISBL (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x07 #endif /* _AVR_IOM8_H_ */

[m8def.inc]	[iom8.h]
;*** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT **************** ;* Created: 2009-11-03 14:40 *** Source: ATmega8.xml ********* ;*********************************************************************** ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y ;* ;* Number : AVR000 ;* File Name : "m8def.inc" ;* Title : Register/Bit Definitions for the ATmega8 ;* Date : 2009-11-03 ;* Version : 2.35 ;* Support E-mail : avr@atmel.com ;* Target MCU : ATmega8 ;* ;* DESCRIPTION ;* When including this file in the assembly program file, all I/O register ;* names and I/O register bit names appearing in the data book can be used. ;* In addition, the six registers forming the three data pointers X, Y and ;* Z have been assigned names XL - ZH. Highest RAM address for Internal ;* SRAM is also defined ;* ;* The Register names are represented by their hexadecimal address. ;* ;* The Register Bit names are represented by their bit number (0-7). ;* ;* Please observe the difference in using the bit names with instructions ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" ;* (skip if bit in register set/cleared). The following example illustrates ;* this: ;* ;* in r16,PORTB ;read PORTB latch ;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) ;* out PORTB,r16 ;output to PORTB ;* ;* in r16,TIFR ;read the Timer Interrupt Flag Register ;* sbrc r16,TOV0 ;test the overflow flag (use bit#) ;* rjmp TOV0_is_set ;jump if set ;* ... ;otherwise do something else ;*********************************************************************** #ifndef _M8DEF_INC_ #define _M8DEF_INC_ #pragma partinc 0 ; * SPECIFY DEVICE *********************************************** .device ATmega8 #pragma AVRPART ADMIN PART_NAME ATmega8 .equ SIGNATURE_000 = 0x1e .equ SIGNATURE_001 = 0x93 .equ SIGNATURE_002 = 0x07 #pragma AVRPART CORE CORE_VERSION V2E ; * I/O REGISTER DEFINITIONS ************************************* ; NOTE: ; Definitions marked "MEMORY MAPPED"are extended I/O ports ; and cannot be used with IN/OUT instructions .equ SREG = 0x3f .equ SPL = 0x3d .equ SPH = 0x3e .equ GICR = 0x3b .equ GIFR = 0x3a .equ TIMSK = 0x39 .equ TIFR = 0x38 .equ SPMCR = 0x37 .equ TWCR = 0x36 .equ MCUCR = 0x35 .equ MCUCSR = 0x34 .equ TCCR0 = 0x33 .equ TCNT0 = 0x32 .equ OSCCAL = 0x31 .equ SFIOR = 0x30 .equ TCCR1A = 0x2f .equ TCCR1B = 0x2e .equ TCNT1L = 0x2c .equ TCNT1H = 0x2d .equ OCR1AL = 0x2a .equ OCR1AH = 0x2b .equ OCR1BL = 0x28 .equ OCR1BH = 0x29 .equ ICR1L = 0x26 .equ ICR1H = 0x27 .equ TCCR2 = 0x25 .equ TCNT2 = 0x24 .equ OCR2 = 0x23 .equ ASSR = 0x22 .equ WDTCR = 0x21 .equ UBRRH = 0x20 .equ UCSRC = 0x20 .equ EEARL = 0x1e .equ EEARH = 0x1f .equ EEDR = 0x1d .equ EECR = 0x1c .equ PORTB = 0x18 .equ DDRB = 0x17 .equ PINB = 0x16 .equ PORTC = 0x15 .equ DDRC = 0x14 .equ PINC = 0x13 .equ PORTD = 0x12 .equ DDRD = 0x11 .equ PIND = 0x10 .equ SPDR = 0x0f .equ SPSR = 0x0e .equ SPCR = 0x0d .equ UDR = 0x0c .equ UCSRA = 0x0b .equ UCSRB = 0x0a .equ UBRRL = 0x09 .equ ACSR = 0x08 .equ ADMUX = 0x07 .equ ADCSRA = 0x06 .equ ADCL = 0x04 .equ ADCH = 0x05 .equ TWDR = 0x03 .equ TWAR = 0x02 .equ TWSR = 0x01 .equ TWBR = 0x00 ; * BIT DEFINITIONS ********************************************** ; * ANALOG_COMPARATOR ******** ; SFIOR - Special Function IO Register .equ ACME = 3 ; Analog Comparator Multiplexer Enable ; ACSR - Analog Comparator Control And Status Register .equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 .equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 .equ ACIC = 2 ; Analog Comparator Input Capture Enable .equ ACIE = 3 ; Analog Comparator Interrupt Enable .equ ACI = 4 ; Analog Comparator Interrupt Flag .equ ACO = 5 ; Analog Compare Output .equ ACBG = 6 ; Analog Comparator Bandgap Select .equ ACD = 7 ; Analog Comparator Disable ; * SPI ********************** ; SPDR - SPI Data Register .equ SPDR0 = 0 ; SPI Data Register bit 0 .equ SPDR1 = 1 ; SPI Data Register bit 1 .equ SPDR2 = 2 ; SPI Data Register bit 2 .equ SPDR3 = 3 ; SPI Data Register bit 3 .equ SPDR4 = 4 ; SPI Data Register bit 4 .equ SPDR5 = 5 ; SPI Data Register bit 5 .equ SPDR6 = 6 ; SPI Data Register bit 6 .equ SPDR7 = 7 ; SPI Data Register bit 7 ; SPSR - SPI Status Register .equ SPI2X = 0 ; Double SPI Speed Bit .equ WCOL = 6 ; Write Collision Flag .equ SPIF = 7 ; SPI Interrupt Flag ; SPCR - SPI Control Register .equ SPR0 = 0 ; SPI Clock Rate Select 0 .equ SPR1 = 1 ; SPI Clock Rate Select 1 .equ CPHA = 2 ; Clock Phase .equ CPOL = 3 ; Clock polarity .equ MSTR = 4 ; Master/Slave Select .equ DORD = 5 ; Data Order .equ SPE = 6 ; SPI Enable .equ SPIE = 7 ; SPI Interrupt Enable ; * EXTERNAL_INTERRUPT ******* ; GICR - General Interrupt Control Register .equ GIMSK = GICR ; For compatibility .equ IVCE = 0 ; Interrupt Vector Change Enable .equ IVSEL = 1 ; Interrupt Vector Select .equ INT0 = 6 ; External Interrupt Request 0 Enable .equ INT1 = 7 ; External Interrupt Request 1 Enable ; GIFR - General Interrupt Flag Register .equ INTF0 = 6 ; External Interrupt Flag 0 .equ INTF1 = 7 ; External Interrupt Flag 1 ; MCUCR - MCU Control Register .equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 .equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 .equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 .equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 ; * TIMER_COUNTER_0 ********** ; TIMSK - Timer/Counter Interrupt Mask Register .equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable ; TIFR - Timer/Counter Interrupt Flag register .equ TOV0 = 0 ; Timer/Counter0 Overflow Flag ; TCCR0 - Timer/Counter0 Control Register .equ CS00 = 0 ; Clock Select0 bit 0 .equ CS01 = 1 ; Clock Select0 bit 1 .equ CS02 = 2 ; Clock Select0 bit 2 ; TCNT0 - Timer Counter 0 .equ TCNT00 = 0 ; Timer Counter 0 bit 0 .equ TCNT01 = 1 ; Timer Counter 0 bit 1 .equ TCNT02 = 2 ; Timer Counter 0 bit 2 .equ TCNT03 = 3 ; Timer Counter 0 bit 3 .equ TCNT04 = 4 ; Timer Counter 0 bit 4 .equ TCNT05 = 5 ; Timer Counter 0 bit 5 .equ TCNT06 = 6 ; Timer Counter 0 bit 6 .equ TCNT07 = 7 ; Timer Counter 0 bit 7 ; * TIMER_COUNTER_1 ********** ; TIMSK - Timer/Counter Interrupt Mask Register .equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable .equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable .equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable .equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable ; TIFR - Timer/Counter Interrupt Flag register .equ TOV1 = 2 ; Timer/Counter1 Overflow Flag .equ OCF1B = 3 ; Output Compare Flag 1B .equ OCF1A = 4 ; Output Compare Flag 1A .equ ICF1 = 5 ; Input Capture Flag 1 ; TCCR1A - Timer/Counter1 Control Register A .equ WGM10 = 0 ; Waveform Generation Mode .equ PWM10 = WGM10 ; For compatibility .equ WGM11 = 1 ; Waveform Generation Mode .equ PWM11 = WGM11 ; For compatibility .equ FOC1B = 2 ; Force Output Compare 1B .equ FOC1A = 3 ; Force Output Compare 1A .equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 .equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 .equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0 .equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 ; TCCR1B - Timer/Counter1 Control Register B .equ CS10 = 0 ; Prescaler source of Timer/Counter 1 .equ CS11 = 1 ; Prescaler source of Timer/Counter 1 .equ CS12 = 2 ; Prescaler source of Timer/Counter 1 .equ WGM12 = 3 ; Waveform Generation Mode .equ CTC10 = WGM12 ; For compatibility .equ CTC1 = WGM12 ; For compatibility .equ WGM13 = 4 ; Waveform Generation Mode .equ CTC11 = WGM13 ; For compatibility .equ ICES1 = 6 ; Input Capture 1 Edge Select .equ ICNC1 = 7 ; Input Capture 1 Noise Canceler ; * TIMER_COUNTER_2 ********** ; TIMSK - Timer/Counter Interrupt Mask register .equ TOIE2 = 6 ; Timer/Counter2 Overflow Interrupt Enable .equ OCIE2 = 7 ; Timer/Counter2 Output Compare Match Interrupt Enable ; TIFR - Timer/Counter Interrupt Flag Register .equ TOV2 = 6 ; Timer/Counter2 Overflow Flag .equ OCF2 = 7 ; Output Compare Flag 2 ; TCCR2 - Timer/Counter2 Control Register .equ CS20 = 0 ; Clock Select bit 0 .equ CS21 = 1 ; Clock Select bit 1 .equ CS22 = 2 ; Clock Select bit 2 .equ WGM21 = 3 ; Waveform Generation Mode .equ CTC2 = WGM21 ; For compatibility .equ COM20 = 4 ; Compare Output Mode bit 0 .equ COM21 = 5 ; Compare Output Mode bit 1 .equ WGM20 = 6 ; Waveform Genration Mode .equ PWM2 = WGM20 ; For compatibility .equ FOC2 = 7 ; Force Output Compare ; TCNT2 - Timer/Counter2 .equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 .equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 .equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 .equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 .equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 .equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 .equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 .equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 ; OCR2 - Timer/Counter2 Output Compare Register .equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 .equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 .equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 .equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 .equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 .equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 .equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 .equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 ; ASSR - Asynchronous Status Register .equ TCR2UB = 0 ; Timer/counter Control Register2 Update Busy .equ OCR2UB = 1 ; Output Compare Register2 Update Busy .equ TCN2UB = 2 ; Timer/Counter2 Update Busy .equ AS2 = 3 ; Asynchronous Timer/counter2 ; SFIOR - Special Function IO Register .equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 ; * USART ******************** ; UDR - USART I/O Data Register .equ UDR0 = 0 ; USART I/O Data Register bit 0 .equ UDR1 = 1 ; USART I/O Data Register bit 1 .equ UDR2 = 2 ; USART I/O Data Register bit 2 .equ UDR3 = 3 ; USART I/O Data Register bit 3 .equ UDR4 = 4 ; USART I/O Data Register bit 4 .equ UDR5 = 5 ; USART I/O Data Register bit 5 .equ UDR6 = 6 ; USART I/O Data Register bit 6 .equ UDR7 = 7 ; USART I/O Data Register bit 7 ; UCSRA - USART Control and Status Register A .equ USR = UCSRA ; For compatibility .equ MPCM = 0 ; Multi-processor Communication Mode .equ U2X = 1 ; Double the USART transmission speed .equ UPE = 2 ; Parity Error .equ PE = UPE ; For compatibility .equ DOR = 3 ; Data overRun .equ FE = 4 ; Framing Error .equ UDRE = 5 ; USART Data Register Empty .equ TXC = 6 ; USART Transmitt Complete .equ RXC = 7 ; USART Receive Complete ; UCSRB - USART Control and Status Register B .equ UCR = UCSRB ; For compatibility .equ TXB8 = 0 ; Transmit Data Bit 8 .equ RXB8 = 1 ; Receive Data Bit 8 .equ UCSZ2 = 2 ; Character Size .equ CHR9 = UCSZ2 ; For compatibility .equ TXEN = 3 ; Transmitter Enable .equ RXEN = 4 ; Receiver Enable .equ UDRIE = 5 ; USART Data register Empty Interrupt Enable .equ TXCIE = 6 ; TX Complete Interrupt Enable .equ RXCIE = 7 ; RX Complete Interrupt Enable ; UCSRC - USART Control and Status Register C .equ UCPOL = 0 ; Clock Polarity .equ UCSZ0 = 1 ; Character Size .equ UCSZ1 = 2 ; Character Size .equ USBS = 3 ; Stop Bit Select .equ UPM0 = 4 ; Parity Mode Bit 0 .equ UPM1 = 5 ; Parity Mode Bit 1 .equ UMSEL = 6 ; USART Mode Select .equ URSEL = 7 ; Register Select .equ UBRRHI = UBRRH ; For compatibility ; * TWI ********************** ; TWBR - TWI Bit Rate register .equ I2BR = TWBR ; For compatibility .equ TWBR0 = 0 ; .equ TWBR1 = 1 ; .equ TWBR2 = 2 ; .equ TWBR3 = 3 ; .equ TWBR4 = 4 ; .equ TWBR5 = 5 ; .equ TWBR6 = 6 ; .equ TWBR7 = 7 ; ; TWCR - TWI Control Register .equ I2CR = TWCR ; For compatibility .equ TWIE = 0 ; TWI Interrupt Enable .equ I2IE = TWIE ; For compatibility .equ TWEN = 2 ; TWI Enable Bit .equ I2EN = TWEN ; For compatibility .equ ENI2C = TWEN ; For compatibility .equ TWWC = 3 ; TWI Write Collition Flag .equ I2WC = TWWC ; For compatibility .equ TWSTO = 4 ; TWI Stop Condition Bit .equ I2STO = TWSTO ; For compatibility .equ TWSTA = 5 ; TWI Start Condition Bit .equ I2STA = TWSTA ; For compatibility .equ TWEA = 6 ; TWI Enable Acknowledge Bit .equ I2EA = TWEA ; For compatibility .equ TWINT = 7 ; TWI Interrupt Flag .equ I2INT = TWINT ; For compatibility ; TWSR - TWI Status Register .equ I2SR = TWSR ; For compatibility .equ TWPS0 = 0 ; TWI Prescaler .equ TWS0 = TWPS0 ; For compatibility .equ I2GCE = TWPS0 ; For compatibility .equ TWPS1 = 1 ; TWI Prescaler .equ TWS1 = TWPS1 ; For compatibility .equ TWS3 = 3 ; TWI Status .equ I2S3 = TWS3 ; For compatibility .equ TWS4 = 4 ; TWI Status .equ I2S4 = TWS4 ; For compatibility .equ TWS5 = 5 ; TWI Status .equ I2S5 = TWS5 ; For compatibility .equ TWS6 = 6 ; TWI Status .equ I2S6 = TWS6 ; For compatibility .equ TWS7 = 7 ; TWI Status .equ I2S7 = TWS7 ; For compatibility ; TWDR - TWI Data register .equ I2DR = TWDR ; For compatibility .equ TWD0 = 0 ; TWI Data Register Bit 0 .equ TWD1 = 1 ; TWI Data Register Bit 1 .equ TWD2 = 2 ; TWI Data Register Bit 2 .equ TWD3 = 3 ; TWI Data Register Bit 3 .equ TWD4 = 4 ; TWI Data Register Bit 4 .equ TWD5 = 5 ; TWI Data Register Bit 5 .equ TWD6 = 6 ; TWI Data Register Bit 6 .equ TWD7 = 7 ; TWI Data Register Bit 7 ; TWAR - TWI (Slave) Address register .equ I2AR = TWAR ; For compatibility .equ TWGCE = 0 ; TWI General Call Recognition Enable Bit .equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 .equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 .equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 .equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 .equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 .equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 .equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 ; * WATCHDOG ***************** ; WDTCR - Watchdog Timer Control Register .equ WDTCSR = WDTCR ; For compatibility .equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 .equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 .equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 .equ WDE = 3 ; Watch Dog Enable .equ WDCE = 4 ; Watchdog Change Enable .equ WDTOE = WDCE ; For compatibility ; * PORTB ******************** ; PORTB - Port B Data Register .equ PORTB0 = 0 ; Port B Data Register bit 0 .equ PB0 = 0 ; For compatibility .equ PORTB1 = 1 ; Port B Data Register bit 1 .equ PB1 = 1 ; For compatibility .equ PORTB2 = 2 ; Port B Data Register bit 2 .equ PB2 = 2 ; For compatibility .equ PORTB3 = 3 ; Port B Data Register bit 3 .equ PB3 = 3 ; For compatibility .equ PORTB4 = 4 ; Port B Data Register bit 4 .equ PB4 = 4 ; For compatibility .equ PORTB5 = 5 ; Port B Data Register bit 5 .equ PB5 = 5 ; For compatibility .equ PORTB6 = 6 ; Port B Data Register bit 6 .equ PB6 = 6 ; For compatibility .equ PORTB7 = 7 ; Port B Data Register bit 7 .equ PB7 = 7 ; For compatibility ; DDRB - Port B Data Direction Register .equ DDB0 = 0 ; Port B Data Direction Register bit 0 .equ DDB1 = 1 ; Port B Data Direction Register bit 1 .equ DDB2 = 2 ; Port B Data Direction Register bit 2 .equ DDB3 = 3 ; Port B Data Direction Register bit 3 .equ DDB4 = 4 ; Port B Data Direction Register bit 4 .equ DDB5 = 5 ; Port B Data Direction Register bit 5 .equ DDB6 = 6 ; Port B Data Direction Register bit 6 .equ DDB7 = 7 ; Port B Data Direction Register bit 7 ; PINB - Port B Input Pins .equ PINB0 = 0 ; Port B Input Pins bit 0 .equ PINB1 = 1 ; Port B Input Pins bit 1 .equ PINB2 = 2 ; Port B Input Pins bit 2 .equ PINB3 = 3 ; Port B Input Pins bit 3 .equ PINB4 = 4 ; Port B Input Pins bit 4 .equ PINB5 = 5 ; Port B Input Pins bit 5 .equ PINB6 = 6 ; Port B Input Pins bit 6 .equ PINB7 = 7 ; Port B Input Pins bit 7 ; * PORTC ******************** ; PORTC - Port C Data Register .equ PORTC0 = 0 ; Port C Data Register bit 0 .equ PC0 = 0 ; For compatibility .equ PORTC1 = 1 ; Port C Data Register bit 1 .equ PC1 = 1 ; For compatibility .equ PORTC2 = 2 ; Port C Data Register bit 2 .equ PC2 = 2 ; For compatibility .equ PORTC3 = 3 ; Port C Data Register bit 3 .equ PC3 = 3 ; For compatibility .equ PORTC4 = 4 ; Port C Data Register bit 4 .equ PC4 = 4 ; For compatibility .equ PORTC5 = 5 ; Port C Data Register bit 5 .equ PC5 = 5 ; For compatibility .equ PORTC6 = 6 ; Port C Data Register bit 6 .equ PC6 = 6 ; For compatibility ; DDRC - Port C Data Direction Register .equ DDC0 = 0 ; Port C Data Direction Register bit 0 .equ DDC1 = 1 ; Port C Data Direction Register bit 1 .equ DDC2 = 2 ; Port C Data Direction Register bit 2 .equ DDC3 = 3 ; Port C Data Direction Register bit 3 .equ DDC4 = 4 ; Port C Data Direction Register bit 4 .equ DDC5 = 5 ; Port C Data Direction Register bit 5 .equ DDC6 = 6 ; Port C Data Direction Register bit 6 ; PINC - Port C Input Pins .equ PINC0 = 0 ; Port C Input Pins bit 0 .equ PINC1 = 1 ; Port C Input Pins bit 1 .equ PINC2 = 2 ; Port C Input Pins bit 2 .equ PINC3 = 3 ; Port C Input Pins bit 3 .equ PINC4 = 4 ; Port C Input Pins bit 4 .equ PINC5 = 5 ; Port C Input Pins bit 5 .equ PINC6 = 6 ; Port C Input Pins bit 6 ; * PORTD ******************** ; PORTD - Port D Data Register .equ PORTD0 = 0 ; Port D Data Register bit 0 .equ PD0 = 0 ; For compatibility .equ PORTD1 = 1 ; Port D Data Register bit 1 .equ PD1 = 1 ; For compatibility .equ PORTD2 = 2 ; Port D Data Register bit 2 .equ PD2 = 2 ; For compatibility .equ PORTD3 = 3 ; Port D Data Register bit 3 .equ PD3 = 3 ; For compatibility .equ PORTD4 = 4 ; Port D Data Register bit 4 .equ PD4 = 4 ; For compatibility .equ PORTD5 = 5 ; Port D Data Register bit 5 .equ PD5 = 5 ; For compatibility .equ PORTD6 = 6 ; Port D Data Register bit 6 .equ PD6 = 6 ; For compatibility .equ PORTD7 = 7 ; Port D Data Register bit 7 .equ PD7 = 7 ; For compatibility ; DDRD - Port D Data Direction Register .equ DDD0 = 0 ; Port D Data Direction Register bit 0 .equ DDD1 = 1 ; Port D Data Direction Register bit 1 .equ DDD2 = 2 ; Port D Data Direction Register bit 2 .equ DDD3 = 3 ; Port D Data Direction Register bit 3 .equ DDD4 = 4 ; Port D Data Direction Register bit 4 .equ DDD5 = 5 ; Port D Data Direction Register bit 5 .equ DDD6 = 6 ; Port D Data Direction Register bit 6 .equ DDD7 = 7 ; Port D Data Direction Register bit 7 ; PIND - Port D Input Pins .equ PIND0 = 0 ; Port D Input Pins bit 0 .equ PIND1 = 1 ; Port D Input Pins bit 1 .equ PIND2 = 2 ; Port D Input Pins bit 2 .equ PIND3 = 3 ; Port D Input Pins bit 3 .equ PIND4 = 4 ; Port D Input Pins bit 4 .equ PIND5 = 5 ; Port D Input Pins bit 5 .equ PIND6 = 6 ; Port D Input Pins bit 6 .equ PIND7 = 7 ; Port D Input Pins bit 7 ; * EEPROM ******************* ; EEDR - EEPROM Data Register .equ EEDR0 = 0 ; EEPROM Data Register bit 0 .equ EEDR1 = 1 ; EEPROM Data Register bit 1 .equ EEDR2 = 2 ; EEPROM Data Register bit 2 .equ EEDR3 = 3 ; EEPROM Data Register bit 3 .equ EEDR4 = 4 ; EEPROM Data Register bit 4 .equ EEDR5 = 5 ; EEPROM Data Register bit 5 .equ EEDR6 = 6 ; EEPROM Data Register bit 6 .equ EEDR7 = 7 ; EEPROM Data Register bit 7 ; EECR - EEPROM Control Register .equ EERE = 0 ; EEPROM Read Enable .equ EEWE = 1 ; EEPROM Write Enable .equ EEMWE = 2 ; EEPROM Master Write Enable .equ EEWEE = EEMWE ; For compatibility .equ EERIE = 3 ; EEPROM Ready Interrupt Enable ; * CPU ********************** ; SREG - Status Register .equ SREG_C = 0 ; Carry Flag .equ SREG_Z = 1 ; Zero Flag .equ SREG_N = 2 ; Negative Flag .equ SREG_V = 3 ; Two's Complement Overflow Flag .equ SREG_S = 4 ; Sign Bit .equ SREG_H = 5 ; Half Carry Flag .equ SREG_T = 6 ; Bit Copy Storage .equ SREG_I = 7 ; Global Interrupt Enable ; MCUCR - MCU Control Register ;.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 ;.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 ;.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 ;.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 .equ SM0 = 4 ; Sleep Mode Select .equ SM1 = 5 ; Sleep Mode Select .equ SM2 = 6 ; Sleep Mode Select .equ SE = 7 ; Sleep Enable ; MCUCSR - MCU Control And Status Register .equ MCUSR = MCUCSR ; For compatibility .equ PORF = 0 ; Power-on reset flag .equ EXTRF = 1 ; External Reset Flag .equ BORF = 2 ; Brown-out Reset Flag .equ WDRF = 3 ; Watchdog Reset Flag ; OSCCAL - Oscillator Calibration Value .equ CAL0 = 0 ; Oscillator Calibration Value Bit0 .equ CAL1 = 1 ; Oscillator Calibration Value Bit1 .equ CAL2 = 2 ; Oscillator Calibration Value Bit2 .equ CAL3 = 3 ; Oscillator Calibration Value Bit3 .equ CAL4 = 4 ; Oscillator Calibration Value Bit4 .equ CAL5 = 5 ; Oscillator Calibration Value Bit5 .equ CAL6 = 6 ; Oscillator Calibration Value Bit6 .equ CAL7 = 7 ; Oscillator Calibration Value Bit7 ; SPMCR - Store Program Memory Control Register .equ SPMEN = 0 ; Store Program Memory Enable .equ PGERS = 1 ; Page Erase .equ PGWRT = 2 ; Page Write .equ BLBSET = 3 ; Boot Lock Bit Set .equ RWWSRE = 4 ; Read-While-Write Section Read Enable .equ RWWSB = 6 ; Read-While-Write Section Busy .equ SPMIE = 7 ; SPM Interrupt Enable ; SFIOR - Special Function IO Register .equ PSR10 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 .equ PUD = 2 ; Pull-up Disable .equ ADHSM = 4 ; ADC High Speed Mode ; * AD_CONVERTER ************* ; ADMUX - The ADC multiplexer Selection Register .equ MUX0 = 0 ; Analog Channel and Gain Selection Bits .equ MUX1 = 1 ; Analog Channel and Gain Selection Bits .equ MUX2 = 2 ; Analog Channel and Gain Selection Bits .equ MUX3 = 3 ; Analog Channel and Gain Selection Bits .equ ADLAR = 5 ; Left Adjust Result .equ REFS0 = 6 ; Reference Selection Bit 0 .equ REFS1 = 7 ; Reference Selection Bit 1 ; ADCSRA - The ADC Control and Status register .equ ADCSR = ADCSRA ; For compatibility .equ ADPS0 = 0 ; ADC Prescaler Select Bits .equ ADPS1 = 1 ; ADC Prescaler Select Bits .equ ADPS2 = 2 ; ADC Prescaler Select Bits .equ ADIE = 3 ; ADC Interrupt Enable .equ ADIF = 4 ; ADC Interrupt Flag .equ ADFR = 5 ; ADC Free Running Select .equ ADSC = 6 ; ADC Start Conversion .equ ADEN = 7 ; ADC Enable ; * LOCKSBITS **************************************************** .equ LB1 = 0 ; Lock bit .equ LB2 = 1 ; Lock bit .equ BLB01 = 2 ; Boot Lock bit .equ BLB02 = 3 ; Boot Lock bit .equ BLB11 = 4 ; Boot lock bit .equ BLB12 = 5 ; Boot lock bit ; * FUSES ******************************************************** ; LOW fuse bits .equ CKSEL0 = 0 ; Select Clock Source .equ CKSEL1 = 1 ; Select Clock Source .equ CKSEL2 = 2 ; Select Clock Source .equ CKSEL3 = 3 ; Select Clock Source .equ SUT0 = 4 ; Select start-up time .equ SUT1 = 5 ; Select start-up time .equ BODEN = 6 ; Brown out detector enable .equ BODLEVEL = 7 ; Brown out detector trigger level ; HIGH fuse bits .equ BOOTRST = 0 ; Select Reset Vector .equ BOOTSZ0 = 1 ; Select Boot Size .equ BOOTSZ1 = 2 ; Select Boot Size .equ EESAVE = 3 ; EEPROM memory is preserved through chip erase .equ CKOPT = 4 ; Oscillator Options .equ SPIEN = 5 ; Enable Serial programming and Data Downloading .equ WTDON = 6 ; Enable watchdog .equ RSTDISBL = 7 ; Disable reset ; * CPU REGISTER DEFINITIONS ************************************* .def XH = r27 .def XL = r26 .def YH = r29 .def YL = r28 .def ZH = r31 .def ZL = r30 ; * DATA MEMORY DECLARATIONS ************************************* .equ FLASHEND = 0x0fff ; Note: Word address .equ IOEND = 0x003f .equ SRAM_START = 0x0060 .equ SRAM_SIZE = 1024 .equ RAMEND = 0x045f .equ XRAMEND = 0x0000 .equ E2END = 0x01ff .equ EEPROMEND = 0x01ff .equ EEADRBITS = 9 #pragma AVRPART MEMORY PROG_FLASH 8192 #pragma AVRPART MEMORY EEPROM 512 #pragma AVRPART MEMORY INT_SRAM SIZE 1024 #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 ; * BOOTLOADER DECLARATIONS ************************************** .equ NRWW_START_ADDR = 0xc00 .equ NRWW_STOP_ADDR = 0xfff .equ RWW_START_ADDR = 0x0 .equ RWW_STOP_ADDR = 0xbff .equ PAGESIZE = 32 .equ FIRSTBOOTSTART = 0xf80 .equ SECONDBOOTSTART = 0xf00 .equ THIRDBOOTSTART = 0xe00 .equ FOURTHBOOTSTART = 0xc00 .equ SMALLBOOTSTART = FIRSTBOOTSTART .equ LARGEBOOTSTART = FOURTHBOOTSTART ; * INTERRUPT VECTORS ********************************************** .equ INT0addr = 0x0001 ; External Interrupt Request 0 .equ INT1addr = 0x0002 ; External Interrupt Request 1 .equ OC2addr = 0x0003 ; Timer/Counter2 Compare Match .equ OVF2addr = 0x0004 ; Timer/Counter2 Overflow .equ ICP1addr = 0x0005 ; Timer/Counter1 Capture Event .equ OC1Aaddr = 0x0006 ; Timer/Counter1 Compare Match A .equ OC1Baddr = 0x0007 ; Timer/Counter1 Compare Match B .equ OVF1addr = 0x0008 ; Timer/Counter1 Overflow .equ OVF0addr = 0x0009 ; Timer/Counter0 Overflow .equ SPIaddr = 0x000a ; Serial Transfer Complete .equ URXCaddr = 0x000b ; USART, Rx Complete .equ UDREaddr = 0x000c ; USART Data Register Empty .equ UTXCaddr = 0x000d ; USART, Tx Complete .equ ADCCaddr = 0x000e ; ADC Conversion Complete .equ ERDYaddr = 0x000f ; EEPROM Ready .equ ACIaddr = 0x0010 ; Analog Comparator .equ TWIaddr = 0x0011 ; 2-wire Serial Interface .equ SPMRaddr = 0x0012 ; Store Program Memory Ready .equ INT_VECTORS_SIZE = 19 ; size in words #pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break #endif /* _M8DEF_INC_ / ; ** END OF FILE ****************************************************	/* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. / / $Id: iom8.h,v 1.14.2.7 2009/02/11 18:05:30 arcanum Exp $ / / avr/iom8.h - definitions for ATmega8 / #ifndef _AVR_IOM8_H_ #define _AVR_IOM8_H_ 1 / This file should only be included from <avr/io.h>, never directly. / #ifndef _AVR_IO_H_ # error "Include <avr/io.h> instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom8.h" #else # error "Attempt to include more than one <avr/ioXXX.h> file." #endif / I/O registers / / TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" / #define TWBR _SFR_IO8(0x00) #define TWSR _SFR_IO8(0x01) #define TWAR _SFR_IO8(0x02) #define TWDR _SFR_IO8(0x03) / ADC / #define ADCW _SFR_IO16(0x04) #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) #define ADCSR _SFR_IO8(0x06) #define ADCSRA _SFR_IO8(0x06) / Changed in 2486H-AVR-09/02 / #define ADMUX _SFR_IO8(0x07) / analog comparator / #define ACSR _SFR_IO8(0x08) / USART / #define UBRRL _SFR_IO8(0x09) #define UCSRB _SFR_IO8(0x0A) #define UCSRA _SFR_IO8(0x0B) #define UDR _SFR_IO8(0x0C) / SPI / #define SPCR _SFR_IO8(0x0D) #define SPSR _SFR_IO8(0x0E) #define SPDR _SFR_IO8(0x0F) / Port D / #define PIND _SFR_IO8(0x10) #define DDRD _SFR_IO8(0x11) #define PORTD _SFR_IO8(0x12) / Port C / #define PINC _SFR_IO8(0x13) #define DDRC _SFR_IO8(0x14) #define PORTC _SFR_IO8(0x15) / Port B / #define PINB _SFR_IO8(0x16) #define DDRB _SFR_IO8(0x17) #define PORTB _SFR_IO8(0x18) / EEPROM Control Register / #define EECR _SFR_IO8(0x1C) / EEPROM Data Register / #define EEDR _SFR_IO8(0x1D) / EEPROM Address Register / #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEARH _SFR_IO8(0x1F) #define UCSRC _SFR_IO8(0x20) #define UBRRH _SFR_IO8(0x20) #define WDTCR _SFR_IO8(0x21) #define ASSR _SFR_IO8(0x22) / Timer 2 / #define OCR2 _SFR_IO8(0x23) #define TCNT2 _SFR_IO8(0x24) #define TCCR2 _SFR_IO8(0x25) / Timer 1 / #define ICR1 _SFR_IO16(0x26) #define ICR1L _SFR_IO8(0x26) #define ICR1H _SFR_IO8(0x27) #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) #define TCCR1B _SFR_IO8(0x2E) #define TCCR1A _SFR_IO8(0x2F) #define SFIOR _SFR_IO8(0x30) #define OSCCAL _SFR_IO8(0x31) / Timer 0 / #define TCNT0 _SFR_IO8(0x32) #define TCCR0 _SFR_IO8(0x33) #define MCUCSR _SFR_IO8(0x34) #define MCUSR _SFR_IO8(0x34) / Defined as an alias for MCUCSR. / #define MCUCR _SFR_IO8(0x35) #define TWCR _SFR_IO8(0x36) #define SPMCR _SFR_IO8(0x37) #define TIFR _SFR_IO8(0x38) #define TIMSK _SFR_IO8(0x39) #define GIFR _SFR_IO8(0x3A) #define GIMSK _SFR_IO8(0x3B) #define GICR _SFR_IO8(0x3B) / Changed in 2486H-AVR-09/02 / / 0x3C reserved (OCR0?) / / 0x3D..0x3E SP / / 0x3F SREG / / Interrupt vectors / / External Interrupt Request 0 / #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) / External Interrupt Request 1 / #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) / Timer/Counter2 Compare Match / #define TIMER2_COMP_vect _VECTOR(3) #define SIG_OUTPUT_COMPARE2 _VECTOR(3) / Timer/Counter2 Overflow / #define TIMER2_OVF_vect _VECTOR(4) #define SIG_OVERFLOW2 _VECTOR(4) / Timer/Counter1 Capture Event / #define TIMER1_CAPT_vect _VECTOR(5) #define SIG_INPUT_CAPTURE1 _VECTOR(5) / Timer/Counter1 Compare Match A / #define TIMER1_COMPA_vect _VECTOR(6) #define SIG_OUTPUT_COMPARE1A _VECTOR(6) / Timer/Counter1 Compare Match B / #define TIMER1_COMPB_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1B _VECTOR(7) / Timer/Counter1 Overflow / #define TIMER1_OVF_vect _VECTOR(8) #define SIG_OVERFLOW1 _VECTOR(8) / Timer/Counter0 Overflow / #define TIMER0_OVF_vect _VECTOR(9) #define SIG_OVERFLOW0 _VECTOR(9) / Serial Transfer Complete / #define SPI_STC_vect _VECTOR(10) #define SIG_SPI _VECTOR(10) / USART, Rx Complete / #define USART_RXC_vect _VECTOR(11) #define SIG_UART_RECV _VECTOR(11) / USART Data Register Empty / #define USART_UDRE_vect _VECTOR(12) #define SIG_UART_DATA _VECTOR(12) / USART, Tx Complete / #define USART_TXC_vect _VECTOR(13) #define SIG_UART_TRANS _VECTOR(13) / ADC Conversion Complete / #define ADC_vect _VECTOR(14) #define SIG_ADC _VECTOR(14) / EEPROM Ready / #define EE_RDY_vect _VECTOR(15) #define SIG_EEPROM_READY _VECTOR(15) / Analog Comparator / #define ANA_COMP_vect _VECTOR(16) #define SIG_COMPARATOR _VECTOR(16) / 2-wire Serial Interface / #define TWI_vect _VECTOR(17) #define SIG_2WIRE_SERIAL _VECTOR(17) / Store Program Memory Ready / #define SPM_RDY_vect _VECTOR(18) #define SIG_SPM_READY _VECTOR(18) #define _VECTORS_SIZE 38 / Bit numbers / / GIMSK / GICR / #define INT1 7 #define INT0 6 #define IVSEL 1 #define IVCE 0 / GIFR / #define INTF1 7 #define INTF0 6 / TIMSK / #define OCIE2 7 #define TOIE2 6 #define TICIE1 5 #define OCIE1A 4 #define OCIE1B 3 #define TOIE1 2 / bit 1 reserved (OCIE0?) / #define TOIE0 0 / TIFR / #define OCF2 7 #define TOV2 6 #define ICF1 5 #define OCF1A 4 #define OCF1B 3 #define TOV1 2 / bit 1 reserved (OCF0?) / #define TOV0 0 / SPMCR / #define SPMIE 7 #define RWWSB 6 / bit 5 reserved / #define RWWSRE 4 #define BLBSET 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 / TWCR / #define TWINT 7 #define TWEA 6 #define TWSTA 5 #define TWSTO 4 #define TWWC 3 #define TWEN 2 / bit 1 reserved (TWI_TST?) / #define TWIE 0 / TWAR / #define TWA6 7 #define TWA5 6 #define TWA4 5 #define TWA3 4 #define TWA2 3 #define TWA1 2 #define TWA0 1 #define TWGCE 0 / TWSR / #define TWS7 7 #define TWS6 6 #define TWS5 5 #define TWS4 4 #define TWS3 3 / bit 2 reserved / #define TWPS1 1 #define TWPS0 0 / MCUCR / #define SE 7 #define SM2 6 #define SM1 5 #define SM0 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 / MCUCSR / / bits 7-4 reserved / #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 / The ADHSM bit has been removed from all documentation, as being not needed at all since the comparator has proven to be fast enough even without feeding it more power. / / SFIOR / / bits 7-5 reserved / #define ACME 3 #define PUD 2 #define PSR2 1 #define PSR10 0 / TCCR0 / / bits 7-3 reserved / #define CS02 2 #define CS01 1 #define CS00 0 / TCCR2 / #define FOC2 7 #define WGM20 6 #define COM21 5 #define COM20 4 #define WGM21 3 #define CS22 2 #define CS21 1 #define CS20 0 / ASSR / / bits 7-4 reserved / #define AS2 3 #define TCN2UB 2 #define OCR2UB 1 #define TCR2UB 0 / TCCR1A / #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define FOC1A 3 #define FOC1B 2 #define WGM11 1 #define WGM10 0 / TCCR1B / #define ICNC1 7 #define ICES1 6 / bit 5 reserved / #define WGM13 4 #define WGM12 3 #define CS12 2 #define CS11 1 #define CS10 0 / WDTCR / / bits 7-5 reserved / #define WDCE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 / UBRRH / #define URSEL 7 / UCSRC / #define URSEL 7 #define UMSEL 6 #define UPM1 5 #define UPM0 4 #define USBS 3 #define UCSZ1 2 #define UCSZ0 1 #define UCPOL 0 / PORTB / #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 / DDRB / #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 / PINB / #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 / PORTC / #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 / DDRC / #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 / PINC / #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 / PORTD / #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 / DDRD / #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 / PIND / #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 / SPSR / #define SPIF 7 #define WCOL 6 #define SPI2X 0 / SPCR / #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 / UCSRA / #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 #define PE 2 #define U2X 1 #define MPCM 0 / UCSRB / #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define UCSZ2 2 #define RXB8 1 #define TXB8 0 / ACSR / #define ACD 7 #define ACBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 / ADCSR / ADCSRA / #define ADEN 7 #define ADSC 6 #define ADFR 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 / ADMUX / #define REFS1 7 #define REFS0 6 #define ADLAR 5 / bit 4 reserved / #define MUX3 3 #define MUX2 2 #define MUX1 1 #define MUX0 0 / EEPROM Control Register / #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 / Constants / #define SPM_PAGESIZE 64 #define RAMEND 0x45F #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x1FFF / Fuses / #define FUSE_MEMORY_SIZE 2 / Low Fuse Byte / #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_BODEN (unsigned char)~_BV(6) #define FUSE_BODLEVEL (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) / High Fuse Byte / #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_CKOPT (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_WDTON (unsigned char)~_BV(6) #define FUSE_RSTDISBL (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) / Lock Bits / #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST / Signature / #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x07 #endif / _AVR_IOM8_H_ */

ATmega16

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[m16def.inc] [iom16.h]

;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** ;***** Created: 2009-11-03 14:40 ******* Source: ATmega16.xml ************ ;************************************************************************* ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y ;* ;* Number : AVR000 ;* File Name : "m16def.inc" ;* Title : Register/Bit Definitions for the ATmega16 ;* Date : 2009-11-03 ;* Version : 2.35 ;* Support E-mail : avr@atmel.com ;* Target MCU : ATmega16 ;* ;* DESCRIPTION ;* When including this file in the assembly program file, all I/O register ;* names and I/O register bit names appearing in the data book can be used. ;* In addition, the six registers forming the three data pointers X, Y and ;* Z have been assigned names XL - ZH. Highest RAM address for Internal ;* SRAM is also defined ;* ;* The Register names are represented by their hexadecimal address. ;* ;* The Register Bit names are represented by their bit number (0-7). ;* ;* Please observe the difference in using the bit names with instructions ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" ;* (skip if bit in register set/cleared). The following example illustrates ;* this: ;* ;* in r16,PORTB ;read PORTB latch ;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) ;* out PORTB,r16 ;output to PORTB ;* ;* in r16,TIFR ;read the Timer Interrupt Flag Register ;* sbrc r16,TOV0 ;test the overflow flag (use bit#) ;* rjmp TOV0_is_set ;jump if set ;* ... ;otherwise do something else ;************************************************************************* #ifndef _M16DEF_INC_ #define _M16DEF_INC_ #pragma partinc 0 ; ***** SPECIFY DEVICE *************************************************** .device ATmega16 #pragma AVRPART ADMIN PART_NAME ATmega16 .equ SIGNATURE_000 = 0x1e .equ SIGNATURE_001 = 0x94 .equ SIGNATURE_002 = 0x03 #pragma AVRPART CORE CORE_VERSION V2E ; ***** I/O REGISTER DEFINITIONS ***************************************** ; NOTE: ; Definitions marked "MEMORY MAPPED"are extended I/O ports ; and cannot be used with IN/OUT instructions .equ SREG = 0x3f .equ SPL = 0x3d .equ SPH = 0x3e .equ OCR0 = 0x3c .equ GICR = 0x3b .equ GIFR = 0x3a .equ TIMSK = 0x39 .equ TIFR = 0x38 .equ SPMCSR = 0x37 .equ TWCR = 0x36 .equ MCUCR = 0x35 .equ MCUCSR = 0x34 .equ TCCR0 = 0x33 .equ TCNT0 = 0x32 .equ OSCCAL = 0x31 .equ OCDR = 0x31 .equ SFIOR = 0x30 .equ TCCR1A = 0x2f .equ TCCR1B = 0x2e .equ TCNT1L = 0x2c .equ TCNT1H = 0x2d .equ OCR1AL = 0x2a .equ OCR1AH = 0x2b .equ OCR1BL = 0x28 .equ OCR1BH = 0x29 .equ ICR1L = 0x26 .equ ICR1H = 0x27 .equ TCCR2 = 0x25 .equ TCNT2 = 0x24 .equ OCR2 = 0x23 .equ ASSR = 0x22 .equ WDTCR = 0x21 .equ UBRRH = 0x20 .equ UCSRC = 0x20 .equ EEARL = 0x1e .equ EEARH = 0x1f .equ EEDR = 0x1d .equ EECR = 0x1c .equ PORTA = 0x1b .equ DDRA = 0x1a .equ PINA = 0x19 .equ PORTB = 0x18 .equ DDRB = 0x17 .equ PINB = 0x16 .equ PORTC = 0x15 .equ DDRC = 0x14 .equ PINC = 0x13 .equ PORTD = 0x12 .equ DDRD = 0x11 .equ PIND = 0x10 .equ SPDR = 0x0f .equ SPSR = 0x0e .equ SPCR = 0x0d .equ UDR = 0x0c .equ UCSRA = 0x0b .equ UCSRB = 0x0a .equ UBRRL = 0x09 .equ ACSR = 0x08 .equ ADMUX = 0x07 .equ ADCSRA = 0x06 .equ ADCH = 0x05 .equ ADCL = 0x04 .equ TWDR = 0x03 .equ TWAR = 0x02 .equ TWSR = 0x01 .equ TWBR = 0x00 ; ***** BIT DEFINITIONS ************************************************** ; ***** TIMER_COUNTER_0 ************** ; TCCR0 - Timer/Counter Control Register .equ CS00 = 0 ; Clock Select 1 .equ CS01 = 1 ; Clock Select 1 .equ CS02 = 2 ; Clock Select 2 .equ WGM01 = 3 ; Waveform Generation Mode 1 .equ CTC0 = WGM01 ; For compatibility .equ COM00 = 4 ; Compare match Output Mode 0 .equ COM01 = 5 ; Compare Match Output Mode 1 .equ WGM00 = 6 ; Waveform Generation Mode 0 .equ PWM0 = WGM00 ; For compatibility .equ FOC0 = 7 ; Force Output Compare ; TCNT0 - Timer/Counter Register .equ TCNT0_0 = 0 ; .equ TCNT0_1 = 1 ; .equ TCNT0_2 = 2 ; .equ TCNT0_3 = 3 ; .equ TCNT0_4 = 4 ; .equ TCNT0_5 = 5 ; .equ TCNT0_6 = 6 ; .equ TCNT0_7 = 7 ; ; OCR0 - Output Compare Register .equ OCR0_0 = 0 ; .equ OCR0_1 = 1 ; .equ OCR0_2 = 2 ; .equ OCR0_3 = 3 ; .equ OCR0_4 = 4 ; .equ OCR0_5 = 5 ; .equ OCR0_6 = 6 ; .equ OCR0_7 = 7 ; ; TIMSK - Timer/Counter Interrupt Mask Register .equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable .equ OCIE0 = 1 ; Timer/Counter0 Output Compare Match Interrupt register ; TIFR - Timer/Counter Interrupt Flag register .equ TOV0 = 0 ; Timer/Counter0 Overflow Flag .equ OCF0 = 1 ; Output Compare Flag 0 ; SFIOR - Special Function IO Register .equ PSR10 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 ; ***** TIMER_COUNTER_1 ************** ; TIMSK - Timer/Counter Interrupt Mask Register .equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable .equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable .equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable .equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable ; TIFR - Timer/Counter Interrupt Flag register .equ TOV1 = 2 ; Timer/Counter1 Overflow Flag .equ OCF1B = 3 ; Output Compare Flag 1B .equ OCF1A = 4 ; Output Compare Flag 1A .equ ICF1 = 5 ; Input Capture Flag 1 ; TCCR1A - Timer/Counter1 Control Register A .equ WGM10 = 0 ; Waveform Generation Mode .equ PWM10 = WGM10 ; For compatibility .equ WGM11 = 1 ; Waveform Generation Mode .equ PWM11 = WGM11 ; For compatibility .equ FOC1B = 2 ; Force Output Compare 1B .equ FOC1A = 3 ; Force Output Compare 1A .equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 .equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 .equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0 .equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 ; TCCR1B - Timer/Counter1 Control Register B .equ CS10 = 0 ; Prescaler source of Timer/Counter 1 .equ CS11 = 1 ; Prescaler source of Timer/Counter 1 .equ CS12 = 2 ; Prescaler source of Timer/Counter 1 .equ WGM12 = 3 ; Waveform Generation Mode .equ CTC10 = WGM12 ; For compatibility .equ CTC1 = WGM12 ; For compatibility .equ WGM13 = 4 ; Waveform Generation Mode .equ CTC11 = WGM13 ; For compatibility .equ ICES1 = 6 ; Input Capture 1 Edge Select .equ ICNC1 = 7 ; Input Capture 1 Noise Canceler ; ***** EXTERNAL_INTERRUPT *********** ; GICR - General Interrupt Control Register .equ GIMSK = GICR ; For compatibility .equ IVCE = 0 ; Interrupt Vector Change Enable .equ IVSEL = 1 ; Interrupt Vector Select .equ INT2 = 5 ; External Interrupt Request 2 Enable .equ INT0 = 6 ; External Interrupt Request 0 Enable .equ INT1 = 7 ; External Interrupt Request 1 Enable ; GIFR - General Interrupt Flag Register .equ INTF2 = 5 ; External Interrupt Flag 2 .equ INTF0 = 6 ; External Interrupt Flag 0 .equ INTF1 = 7 ; External Interrupt Flag 1 ; MCUCR - General Interrupt Control Register .equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 .equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 .equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 .equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 ; MCUCSR - MCU Control And Status Register .equ ISC2 = 6 ; Interrupt Sense Control 2 ; ***** EEPROM *********************** ; EEDR - EEPROM Data Register .equ EEDR0 = 0 ; EEPROM Data Register bit 0 .equ EEDR1 = 1 ; EEPROM Data Register bit 1 .equ EEDR2 = 2 ; EEPROM Data Register bit 2 .equ EEDR3 = 3 ; EEPROM Data Register bit 3 .equ EEDR4 = 4 ; EEPROM Data Register bit 4 .equ EEDR5 = 5 ; EEPROM Data Register bit 5 .equ EEDR6 = 6 ; EEPROM Data Register bit 6 .equ EEDR7 = 7 ; EEPROM Data Register bit 7 ; EECR - EEPROM Control Register .equ EERE = 0 ; EEPROM Read Enable .equ EEWE = 1 ; EEPROM Write Enable .equ EEMWE = 2 ; EEPROM Master Write Enable .equ EEWEE = EEMWE ; For compatibility .equ EERIE = 3 ; EEPROM Ready Interrupt Enable ; ***** CPU ************************** ; SREG - Status Register .equ SREG_C = 0 ; Carry Flag .equ SREG_Z = 1 ; Zero Flag .equ SREG_N = 2 ; Negative Flag .equ SREG_V = 3 ; Two's Complement Overflow Flag .equ SREG_S = 4 ; Sign Bit .equ SREG_H = 5 ; Half Carry Flag .equ SREG_T = 6 ; Bit Copy Storage .equ SREG_I = 7 ; Global Interrupt Enable ; MCUCR - MCU Control Register ;.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 ;.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 ;.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 ;.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 .equ SM0 = 4 ; Sleep Mode Select .equ SM1 = 5 ; Sleep Mode Select .equ SE = 6 ; Sleep Enable .equ SM2 = 7 ; Sleep Mode Select ; MCUCSR - MCU Control And Status Register .equ MCUSR = MCUCSR ; For compatibility .equ PORF = 0 ; Power-on reset flag .equ EXTRF = 1 ; External Reset Flag .equ EXTREF = EXTRF ; For compatibility .equ BORF = 2 ; Brown-out Reset Flag .equ WDRF = 3 ; Watchdog Reset Flag .equ JTRF = 4 ; JTAG Reset Flag .equ JTD = 7 ; JTAG Interface Disable ; OSCCAL - Oscillator Calibration Value .equ CAL0 = 0 ; Oscillator Calibration Value Bit0 .equ CAL1 = 1 ; Oscillator Calibration Value Bit1 .equ CAL2 = 2 ; Oscillator Calibration Value Bit2 .equ CAL3 = 3 ; Oscillator Calibration Value Bit3 .equ CAL4 = 4 ; Oscillator Calibration Value Bit4 .equ CAL5 = 5 ; Oscillator Calibration Value Bit5 .equ CAL6 = 6 ; Oscillator Calibration Value Bit6 .equ CAL7 = 7 ; Oscillator Calibration Value Bit7 ; SFIOR - Special function I/O register ;.equ PSR10 = 0 ; Prescaler reset .equ PSR2 = 1 ; Prescaler reset .equ PUD = 2 ; Pull-up Disable ; ***** TIMER_COUNTER_2 ************** ; TIMSK - Timer/Counter Interrupt Mask register .equ TOIE2 = 6 ; Timer/Counter2 Overflow Interrupt Enable .equ OCIE2 = 7 ; Timer/Counter2 Output Compare Match Interrupt Enable ; TIFR - Timer/Counter Interrupt Flag Register .equ TOV2 = 6 ; Timer/Counter2 Overflow Flag .equ OCF2 = 7 ; Output Compare Flag 2 ; TCCR2 - Timer/Counter2 Control Register .equ CS20 = 0 ; Clock Select bit 0 .equ CS21 = 1 ; Clock Select bit 1 .equ CS22 = 2 ; Clock Select bit 2 .equ WGM21 = 3 ; Waveform Generation Mode .equ CTC2 = WGM21 ; For compatibility .equ COM20 = 4 ; Compare Output Mode bit 0 .equ COM21 = 5 ; Compare Output Mode bit 1 .equ WGM20 = 6 ; Waveform Genration Mode .equ PWM2 = WGM20 ; For compatibility .equ FOC2 = 7 ; Force Output Compare ; TCNT2 - Timer/Counter2 .equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 .equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 .equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 .equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 .equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 .equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 .equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 .equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 ; OCR2 - Timer/Counter2 Output Compare Register .equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 .equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 .equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 .equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 .equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 .equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 .equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 .equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 ; ASSR - Asynchronous Status Register .equ TCR2UB = 0 ; Timer/counter Control Register2 Update Busy .equ OCR2UB = 1 ; Output Compare Register2 Update Busy .equ TCN2UB = 2 ; Timer/Counter2 Update Busy .equ AS2 = 3 ; Asynchronous Timer/counter2 ; SFIOR - Special Function IO Register ;.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 ; ***** SPI ************************** ; SPDR - SPI Data Register .equ SPDR0 = 0 ; SPI Data Register bit 0 .equ SPDR1 = 1 ; SPI Data Register bit 1 .equ SPDR2 = 2 ; SPI Data Register bit 2 .equ SPDR3 = 3 ; SPI Data Register bit 3 .equ SPDR4 = 4 ; SPI Data Register bit 4 .equ SPDR5 = 5 ; SPI Data Register bit 5 .equ SPDR6 = 6 ; SPI Data Register bit 6 .equ SPDR7 = 7 ; SPI Data Register bit 7 ; SPSR - SPI Status Register .equ SPI2X = 0 ; Double SPI Speed Bit .equ WCOL = 6 ; Write Collision Flag .equ SPIF = 7 ; SPI Interrupt Flag ; SPCR - SPI Control Register .equ SPR0 = 0 ; SPI Clock Rate Select 0 .equ SPR1 = 1 ; SPI Clock Rate Select 1 .equ CPHA = 2 ; Clock Phase .equ CPOL = 3 ; Clock polarity .equ MSTR = 4 ; Master/Slave Select .equ DORD = 5 ; Data Order .equ SPE = 6 ; SPI Enable .equ SPIE = 7 ; SPI Interrupt Enable ; ***** USART ************************ ; UDR - USART I/O Data Register .equ UDR0 = 0 ; USART I/O Data Register bit 0 .equ UDR1 = 1 ; USART I/O Data Register bit 1 .equ UDR2 = 2 ; USART I/O Data Register bit 2 .equ UDR3 = 3 ; USART I/O Data Register bit 3 .equ UDR4 = 4 ; USART I/O Data Register bit 4 .equ UDR5 = 5 ; USART I/O Data Register bit 5 .equ UDR6 = 6 ; USART I/O Data Register bit 6 .equ UDR7 = 7 ; USART I/O Data Register bit 7 ; UCSRA - USART Control and Status Register A .equ USR = UCSRA ; For compatibility .equ MPCM = 0 ; Multi-processor Communication Mode .equ U2X = 1 ; Double the USART transmission speed .equ UPE = 2 ; Parity Error .equ PE = UPE ; For compatibility .equ DOR = 3 ; Data overRun .equ FE = 4 ; Framing Error .equ UDRE = 5 ; USART Data Register Empty .equ TXC = 6 ; USART Transmitt Complete .equ RXC = 7 ; USART Receive Complete ; UCSRB - USART Control and Status Register B .equ UCR = UCSRB ; For compatibility .equ TXB8 = 0 ; Transmit Data Bit 8 .equ RXB8 = 1 ; Receive Data Bit 8 .equ UCSZ2 = 2 ; Character Size .equ CHR9 = UCSZ2 ; For compatibility .equ TXEN = 3 ; Transmitter Enable .equ RXEN = 4 ; Receiver Enable .equ UDRIE = 5 ; USART Data register Empty Interrupt Enable .equ TXCIE = 6 ; TX Complete Interrupt Enable .equ RXCIE = 7 ; RX Complete Interrupt Enable ; UCSRC - USART Control and Status Register C .equ UCPOL = 0 ; Clock Polarity .equ UCSZ0 = 1 ; Character Size .equ UCSZ1 = 2 ; Character Size .equ USBS = 3 ; Stop Bit Select .equ UPM0 = 4 ; Parity Mode Bit 0 .equ UPM1 = 5 ; Parity Mode Bit 1 .equ UMSEL = 6 ; USART Mode Select .equ URSEL = 7 ; Register Select .equ UBRRHI = UBRRH ; For compatibility ; ***** TWI ************************** ; TWBR - TWI Bit Rate register .equ I2BR = TWBR ; For compatibility .equ TWBR0 = 0 ; .equ TWBR1 = 1 ; .equ TWBR2 = 2 ; .equ TWBR3 = 3 ; .equ TWBR4 = 4 ; .equ TWBR5 = 5 ; .equ TWBR6 = 6 ; .equ TWBR7 = 7 ; ; TWCR - TWI Control Register .equ I2CR = TWCR ; For compatibility .equ TWIE = 0 ; TWI Interrupt Enable .equ I2IE = TWIE ; For compatibility .equ TWEN = 2 ; TWI Enable Bit .equ I2EN = TWEN ; For compatibility .equ ENI2C = TWEN ; For compatibility .equ TWWC = 3 ; TWI Write Collition Flag .equ I2WC = TWWC ; For compatibility .equ TWSTO = 4 ; TWI Stop Condition Bit .equ I2STO = TWSTO ; For compatibility .equ TWSTA = 5 ; TWI Start Condition Bit .equ I2STA = TWSTA ; For compatibility .equ TWEA = 6 ; TWI Enable Acknowledge Bit .equ I2EA = TWEA ; For compatibility .equ TWINT = 7 ; TWI Interrupt Flag .equ I2INT = TWINT ; For compatibility ; TWSR - TWI Status Register .equ I2SR = TWSR ; For compatibility .equ TWPS0 = 0 ; TWI Prescaler .equ TWS0 = TWPS0 ; For compatibility .equ I2GCE = TWPS0 ; For compatibility .equ TWPS1 = 1 ; TWI Prescaler .equ TWS1 = TWPS1 ; For compatibility .equ TWS3 = 3 ; TWI Status .equ I2S3 = TWS3 ; For compatibility .equ TWS4 = 4 ; TWI Status .equ I2S4 = TWS4 ; For compatibility .equ TWS5 = 5 ; TWI Status .equ I2S5 = TWS5 ; For compatibility .equ TWS6 = 6 ; TWI Status .equ I2S6 = TWS6 ; For compatibility .equ TWS7 = 7 ; TWI Status .equ I2S7 = TWS7 ; For compatibility ; TWDR - TWI Data register .equ I2DR = TWDR ; For compatibility .equ TWD0 = 0 ; TWI Data Register Bit 0 .equ TWD1 = 1 ; TWI Data Register Bit 1 .equ TWD2 = 2 ; TWI Data Register Bit 2 .equ TWD3 = 3 ; TWI Data Register Bit 3 .equ TWD4 = 4 ; TWI Data Register Bit 4 .equ TWD5 = 5 ; TWI Data Register Bit 5 .equ TWD6 = 6 ; TWI Data Register Bit 6 .equ TWD7 = 7 ; TWI Data Register Bit 7 ; TWAR - TWI (Slave) Address register .equ I2AR = TWAR ; For compatibility .equ TWGCE = 0 ; TWI General Call Recognition Enable Bit .equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 .equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 .equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 .equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 .equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 .equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 .equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 ; ***** ANALOG_COMPARATOR ************ ; SFIOR - Special Function IO Register .equ ACME = 3 ; Analog Comparator Multiplexer Enable ; ACSR - Analog Comparator Control And Status Register .equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 .equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 .equ ACIC = 2 ; Analog Comparator Input Capture Enable .equ ACIE = 3 ; Analog Comparator Interrupt Enable .equ ACI = 4 ; Analog Comparator Interrupt Flag .equ ACO = 5 ; Analog Compare Output .equ ACBG = 6 ; Analog Comparator Bandgap Select .equ ACD = 7 ; Analog Comparator Disable ; ***** AD_CONVERTER ***************** ; ADMUX - The ADC multiplexer Selection Register .equ MUX0 = 0 ; Analog Channel and Gain Selection Bits .equ MUX1 = 1 ; Analog Channel and Gain Selection Bits .equ MUX2 = 2 ; Analog Channel and Gain Selection Bits .equ MUX3 = 3 ; Analog Channel and Gain Selection Bits .equ MUX4 = 4 ; Analog Channel and Gain Selection Bits .equ ADLAR = 5 ; Left Adjust Result .equ REFS0 = 6 ; Reference Selection Bit 0 .equ REFS1 = 7 ; Reference Selection Bit 1 ; ADCSRA - The ADC Control and Status register .equ ADCSR = ADCSRA ; For compatibility .equ ADPS0 = 0 ; ADC Prescaler Select Bits .equ ADPS1 = 1 ; ADC Prescaler Select Bits .equ ADPS2 = 2 ; ADC Prescaler Select Bits .equ ADIE = 3 ; ADC Interrupt Enable .equ ADIF = 4 ; ADC Interrupt Flag .equ ADATE = 5 ; When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset. .equ ADFR = ADATE ; For compatibility .equ ADSC = 6 ; ADC Start Conversion .equ ADEN = 7 ; ADC Enable ; ADCH - ADC Data Register High Byte .equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 .equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 .equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 .equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 .equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 .equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 .equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 .equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 ; ADCL - ADC Data Register Low Byte .equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 .equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 .equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 .equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 .equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 .equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 .equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 .equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 ; SFIOR - Special Function IO Register .equ ADTS0 = 5 ; ADC Auto Trigger Source 0 .equ ADTS1 = 6 ; ADC Auto Trigger Source 1 .equ ADTS2 = 7 ; ADC Auto Trigger Source 2 ; ***** JTAG ************************* ; OCDR - On-Chip Debug Related Register in I/O Memory .equ OCDR0 = 0 ; On-Chip Debug Register Bit 0 .equ OCDR1 = 1 ; On-Chip Debug Register Bit 1 .equ OCDR2 = 2 ; On-Chip Debug Register Bit 2 .equ OCDR3 = 3 ; On-Chip Debug Register Bit 3 .equ OCDR4 = 4 ; On-Chip Debug Register Bit 4 .equ OCDR5 = 5 ; On-Chip Debug Register Bit 5 .equ OCDR6 = 6 ; On-Chip Debug Register Bit 6 .equ OCDR7 = 7 ; On-Chip Debug Register Bit 7 .equ IDRD = OCDR7 ; For compatibility ; MCUCSR - MCU Control And Status Register ;.equ JTRF = 4 ; JTAG Reset Flag ;.equ JTD = 7 ; JTAG Interface Disable ; ***** BOOT_LOAD ******************** ; SPMCSR - Store Program Memory Control Register .equ SPMCR = SPMCSR ; For compatibility .equ SPMEN = 0 ; Store Program Memory Enable .equ PGERS = 1 ; Page Erase .equ PGWRT = 2 ; Page Write .equ BLBSET = 3 ; Boot Lock Bit Set .equ RWWSRE = 4 ; Read While Write section read enable .equ ASRE = RWWSRE ; For compatibility .equ RWWSB = 6 ; Read While Write Section Busy .equ ASB = RWWSB ; For compatibility .equ SPMIE = 7 ; SPM Interrupt Enable ; ***** PORTA ************************ ; PORTA - Port A Data Register .equ PORTA0 = 0 ; Port A Data Register bit 0 .equ PA0 = 0 ; For compatibility .equ PORTA1 = 1 ; Port A Data Register bit 1 .equ PA1 = 1 ; For compatibility .equ PORTA2 = 2 ; Port A Data Register bit 2 .equ PA2 = 2 ; For compatibility .equ PORTA3 = 3 ; Port A Data Register bit 3 .equ PA3 = 3 ; For compatibility .equ PORTA4 = 4 ; Port A Data Register bit 4 .equ PA4 = 4 ; For compatibility .equ PORTA5 = 5 ; Port A Data Register bit 5 .equ PA5 = 5 ; For compatibility .equ PORTA6 = 6 ; Port A Data Register bit 6 .equ PA6 = 6 ; For compatibility .equ PORTA7 = 7 ; Port A Data Register bit 7 .equ PA7 = 7 ; For compatibility ; DDRA - Port A Data Direction Register .equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 .equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 .equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 .equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 .equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 .equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 .equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 .equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 ; PINA - Port A Input Pins .equ PINA0 = 0 ; Input Pins, Port A bit 0 .equ PINA1 = 1 ; Input Pins, Port A bit 1 .equ PINA2 = 2 ; Input Pins, Port A bit 2 .equ PINA3 = 3 ; Input Pins, Port A bit 3 .equ PINA4 = 4 ; Input Pins, Port A bit 4 .equ PINA5 = 5 ; Input Pins, Port A bit 5 .equ PINA6 = 6 ; Input Pins, Port A bit 6 .equ PINA7 = 7 ; Input Pins, Port A bit 7 ; ***** PORTB ************************ ; PORTB - Port B Data Register .equ PORTB0 = 0 ; Port B Data Register bit 0 .equ PB0 = 0 ; For compatibility .equ PORTB1 = 1 ; Port B Data Register bit 1 .equ PB1 = 1 ; For compatibility .equ PORTB2 = 2 ; Port B Data Register bit 2 .equ PB2 = 2 ; For compatibility .equ PORTB3 = 3 ; Port B Data Register bit 3 .equ PB3 = 3 ; For compatibility .equ PORTB4 = 4 ; Port B Data Register bit 4 .equ PB4 = 4 ; For compatibility .equ PORTB5 = 5 ; Port B Data Register bit 5 .equ PB5 = 5 ; For compatibility .equ PORTB6 = 6 ; Port B Data Register bit 6 .equ PB6 = 6 ; For compatibility .equ PORTB7 = 7 ; Port B Data Register bit 7 .equ PB7 = 7 ; For compatibility ; DDRB - Port B Data Direction Register .equ DDB0 = 0 ; Port B Data Direction Register bit 0 .equ DDB1 = 1 ; Port B Data Direction Register bit 1 .equ DDB2 = 2 ; Port B Data Direction Register bit 2 .equ DDB3 = 3 ; Port B Data Direction Register bit 3 .equ DDB4 = 4 ; Port B Data Direction Register bit 4 .equ DDB5 = 5 ; Port B Data Direction Register bit 5 .equ DDB6 = 6 ; Port B Data Direction Register bit 6 .equ DDB7 = 7 ; Port B Data Direction Register bit 7 ; PINB - Port B Input Pins .equ PINB0 = 0 ; Port B Input Pins bit 0 .equ PINB1 = 1 ; Port B Input Pins bit 1 .equ PINB2 = 2 ; Port B Input Pins bit 2 .equ PINB3 = 3 ; Port B Input Pins bit 3 .equ PINB4 = 4 ; Port B Input Pins bit 4 .equ PINB5 = 5 ; Port B Input Pins bit 5 .equ PINB6 = 6 ; Port B Input Pins bit 6 .equ PINB7 = 7 ; Port B Input Pins bit 7 ; ***** PORTC ************************ ; PORTC - Port C Data Register .equ PORTC0 = 0 ; Port C Data Register bit 0 .equ PC0 = 0 ; For compatibility .equ PORTC1 = 1 ; Port C Data Register bit 1 .equ PC1 = 1 ; For compatibility .equ PORTC2 = 2 ; Port C Data Register bit 2 .equ PC2 = 2 ; For compatibility .equ PORTC3 = 3 ; Port C Data Register bit 3 .equ PC3 = 3 ; For compatibility .equ PORTC4 = 4 ; Port C Data Register bit 4 .equ PC4 = 4 ; For compatibility .equ PORTC5 = 5 ; Port C Data Register bit 5 .equ PC5 = 5 ; For compatibility .equ PORTC6 = 6 ; Port C Data Register bit 6 .equ PC6 = 6 ; For compatibility .equ PORTC7 = 7 ; Port C Data Register bit 7 .equ PC7 = 7 ; For compatibility ; DDRC - Port C Data Direction Register .equ DDC0 = 0 ; Port C Data Direction Register bit 0 .equ DDC1 = 1 ; Port C Data Direction Register bit 1 .equ DDC2 = 2 ; Port C Data Direction Register bit 2 .equ DDC3 = 3 ; Port C Data Direction Register bit 3 .equ DDC4 = 4 ; Port C Data Direction Register bit 4 .equ DDC5 = 5 ; Port C Data Direction Register bit 5 .equ DDC6 = 6 ; Port C Data Direction Register bit 6 .equ DDC7 = 7 ; Port C Data Direction Register bit 7 ; PINC - Port C Input Pins .equ PINC0 = 0 ; Port C Input Pins bit 0 .equ PINC1 = 1 ; Port C Input Pins bit 1 .equ PINC2 = 2 ; Port C Input Pins bit 2 .equ PINC3 = 3 ; Port C Input Pins bit 3 .equ PINC4 = 4 ; Port C Input Pins bit 4 .equ PINC5 = 5 ; Port C Input Pins bit 5 .equ PINC6 = 6 ; Port C Input Pins bit 6 .equ PINC7 = 7 ; Port C Input Pins bit 7 ; ***** PORTD ************************ ; PORTD - Port D Data Register .equ PORTD0 = 0 ; Port D Data Register bit 0 .equ PD0 = 0 ; For compatibility .equ PORTD1 = 1 ; Port D Data Register bit 1 .equ PD1 = 1 ; For compatibility .equ PORTD2 = 2 ; Port D Data Register bit 2 .equ PD2 = 2 ; For compatibility .equ PORTD3 = 3 ; Port D Data Register bit 3 .equ PD3 = 3 ; For compatibility .equ PORTD4 = 4 ; Port D Data Register bit 4 .equ PD4 = 4 ; For compatibility .equ PORTD5 = 5 ; Port D Data Register bit 5 .equ PD5 = 5 ; For compatibility .equ PORTD6 = 6 ; Port D Data Register bit 6 .equ PD6 = 6 ; For compatibility .equ PORTD7 = 7 ; Port D Data Register bit 7 .equ PD7 = 7 ; For compatibility ; DDRD - Port D Data Direction Register .equ DDD0 = 0 ; Port D Data Direction Register bit 0 .equ DDD1 = 1 ; Port D Data Direction Register bit 1 .equ DDD2 = 2 ; Port D Data Direction Register bit 2 .equ DDD3 = 3 ; Port D Data Direction Register bit 3 .equ DDD4 = 4 ; Port D Data Direction Register bit 4 .equ DDD5 = 5 ; Port D Data Direction Register bit 5 .equ DDD6 = 6 ; Port D Data Direction Register bit 6 .equ DDD7 = 7 ; Port D Data Direction Register bit 7 ; PIND - Port D Input Pins .equ PIND0 = 0 ; Port D Input Pins bit 0 .equ PIND1 = 1 ; Port D Input Pins bit 1 .equ PIND2 = 2 ; Port D Input Pins bit 2 .equ PIND3 = 3 ; Port D Input Pins bit 3 .equ PIND4 = 4 ; Port D Input Pins bit 4 .equ PIND5 = 5 ; Port D Input Pins bit 5 .equ PIND6 = 6 ; Port D Input Pins bit 6 .equ PIND7 = 7 ; Port D Input Pins bit 7 ; ***** WATCHDOG ********************* ; WDTCR - Watchdog Timer Control Register .equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 .equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 .equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 .equ WDE = 3 ; Watch Dog Enable .equ WDTOE = 4 ; RW .equ WDDE = WDTOE ; For compatibility ; ***** LOCKSBITS ******************************************************** .equ LB1 = 0 ; Lock bit .equ LB2 = 1 ; Lock bit .equ BLB01 = 2 ; Boot Lock bit .equ BLB02 = 3 ; Boot Lock bit .equ BLB11 = 4 ; Boot lock bit .equ BLB12 = 5 ; Boot lock bit ; ***** FUSES ************************************************************ ; LOW fuse bits .equ CKSEL0 = 0 ; Select Clock Source .equ CKSEL1 = 1 ; Select Clock Source .equ CKSEL2 = 2 ; Select Clock Source .equ CKSEL3 = 3 ; Select Clock Source .equ SUT0 = 4 ; Select start-up time .equ SUT1 = 5 ; Select start-up time .equ BODEN = 6 ; Brown out detector enable .equ BODLEVEL = 7 ; Brown out detector trigger level ; HIGH fuse bits .equ BOOTRST = 0 ; Select Reset Vector .equ BOOTSZ0 = 1 ; Select Boot Size .equ BOOTSZ1 = 2 ; Select Boot Size .equ EESAVE = 3 ; EEPROM memory is preserved through chip erase .equ CKOPT = 4 ; Oscillator Options .equ SPIEN = 5 ; Enable Serial programming and Data Downloading .equ JTAGEN = 6 ; Enable JTAG .equ OCDEN = 7 ; Enable OCD ; ***** CPU REGISTER DEFINITIONS ***************************************** .def XH = r27 .def XL = r26 .def YH = r29 .def YL = r28 .def ZH = r31 .def ZL = r30 ; ***** DATA MEMORY DECLARATIONS ***************************************** .equ FLASHEND = 0x1fff ; Note: Word address .equ IOEND = 0x003f .equ SRAM_START = 0x0060 .equ SRAM_SIZE = 1024 .equ RAMEND = 0x045f .equ XRAMEND = 0x0000 .equ E2END = 0x01ff .equ EEPROMEND = 0x01ff .equ EEADRBITS = 9 #pragma AVRPART MEMORY PROG_FLASH 16384 #pragma AVRPART MEMORY EEPROM 512 #pragma AVRPART MEMORY INT_SRAM SIZE 1024 #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 ; ***** BOOTLOADER DECLARATIONS ****************************************** .equ NRWW_START_ADDR = 0x1c00 .equ NRWW_STOP_ADDR = 0x1fff .equ RWW_START_ADDR = 0x0 .equ RWW_STOP_ADDR = 0x1bff .equ PAGESIZE = 64 .equ FIRSTBOOTSTART = 0x1f80 .equ SECONDBOOTSTART = 0x1f00 .equ THIRDBOOTSTART = 0x1e00 .equ FOURTHBOOTSTART = 0x1c00 .equ SMALLBOOTSTART = FIRSTBOOTSTART .equ LARGEBOOTSTART = FOURTHBOOTSTART ; ***** INTERRUPT VECTORS ************************************************ .equ INT0addr = 0x0002 ; External Interrupt Request 0 .equ INT1addr = 0x0004 ; External Interrupt Request 1 .equ OC2addr = 0x0006 ; Timer/Counter2 Compare Match .equ OVF2addr = 0x0008 ; Timer/Counter2 Overflow .equ ICP1addr = 0x000a ; Timer/Counter1 Capture Event .equ OC1Aaddr = 0x000c ; Timer/Counter1 Compare Match A .equ OC1Baddr = 0x000e ; Timer/Counter1 Compare Match B .equ OVF1addr = 0x0010 ; Timer/Counter1 Overflow .equ OVF0addr = 0x0012 ; Timer/Counter0 Overflow .equ SPIaddr = 0x0014 ; Serial Transfer Complete .equ URXCaddr = 0x0016 ; USART, Rx Complete .equ UDREaddr = 0x0018 ; USART Data Register Empty .equ UTXCaddr = 0x001a ; USART, Tx Complete .equ ADCCaddr = 0x001c ; ADC Conversion Complete .equ ERDYaddr = 0x001e ; EEPROM Ready .equ ACIaddr = 0x0020 ; Analog Comparator .equ TWIaddr = 0x0022 ; 2-wire Serial Interface .equ INT2addr = 0x0024 ; External Interrupt Request 2 .equ OC0addr = 0x0026 ; Timer/Counter0 Compare Match .equ SPMRaddr = 0x0028 ; Store Program Memory Ready .equ INT_VECTORS_SIZE = 42 ; size in words #endif /* _M16DEF_INC_ */ ; ***** END OF FILE ****************************************************** /* Copyright (c) 2004 Eric B. Weddington All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom16.h,v 1.14.2.6 2009/02/11 18:05:26 arcanum Exp $ */ /* avr/iom16.h - definitions for ATmega16 */ #ifndef _AVR_IOM16_H_ #define _AVR_IOM16_H_ 1 /* This file should only be included from <avr/io.h>, never directly. */ #ifndef _AVR_IO_H_ # error "Include <avr/io.h> instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom16.h" #else # error "Attempt to include more than one <avr/ioXXX.h> file." #endif /* Registers and associated bit numbers */ #define TWBR _SFR_IO8(0x00) #define TWSR _SFR_IO8(0x01) #define TWPS0 0 #define TWPS1 1 #define TWS3 3 #define TWS4 4 #define TWS5 5 #define TWS6 6 #define TWS7 7 #define TWAR _SFR_IO8(0x02) #define TWGCE 0 #define TWA0 1 #define TWA1 2 #define TWA2 3 #define TWA3 4 #define TWA4 5 #define TWA5 6 #define TWA6 7 #define TWDR _SFR_IO8(0x03) /* Combine ADCL and ADCH */ #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCW _SFR_IO16(0x04) #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) #define ADCSRA _SFR_IO8(0x06) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADMUX _SFR_IO8(0x07) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define ACSR _SFR_IO8(0x08) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define UBRRL _SFR_IO8(0x09) #define UCSRB _SFR_IO8(0x0A) #define TXB8 0 #define RXB8 1 #define UCSZ2 2 #define TXEN 3 #define RXEN 4 #define UDRIE 5 #define TXCIE 6 #define RXCIE 7 #define UCSRA _SFR_IO8(0x0B) #define MPCM 0 #define U2X 1 #define PE 2 #define DOR 3 #define FE 4 #define UDRE 5 #define TXC 6 #define RXC 7 #define UDR _SFR_IO8(0x0C) #define SPCR _SFR_IO8(0x0D) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x0E) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x0F) #define PIND _SFR_IO8(0x10) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x11) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x12) #define PD0 0 #define PD1 1 #define PD2 2 #define PD3 3 #define PD4 4 #define PD5 5 #define PD6 6 #define PD7 7 #define PINC _SFR_IO8(0x13) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define PINC7 7 #define DDRC _SFR_IO8(0x14) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define DDC7 7 #define PORTC _SFR_IO8(0x15) #define PC0 0 #define PC1 1 #define PC2 2 #define PC3 3 #define PC4 4 #define PC5 5 #define PC6 6 #define PC7 7 #define PINB _SFR_IO8(0x16) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x17) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x18) #define PB0 0 #define PB1 1 #define PB2 2 #define PB3 3 #define PB4 4 #define PB5 5 #define PB6 6 #define PB7 7 #define PINA _SFR_IO8(0x19) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define PINA4 4 #define PINA5 5 #define PINA6 6 #define PINA7 7 #define DDRA _SFR_IO8(0x1A) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define DDA4 4 #define DDA5 5 #define DDA6 6 #define DDA7 7 #define PORTA _SFR_IO8(0x1B) #define PA0 0 #define PA1 1 #define PA2 2 #define PA3 3 #define PA4 4 #define PA5 5 #define PA6 6 #define PA7 7 /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) #define EERE 0 #define EEWE 1 #define EEMWE 2 #define EERIE 3 /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEARH _SFR_IO8(0x1F) #define UCSRC _SFR_IO8(0x20) #define UCPOL 0 #define UCSZ0 1 #define UCSZ1 2 #define USBS 3 #define UPM0 4 #define UPM1 5 #define UMSEL 6 #define URSEL 7 #define UBRRH _SFR_IO8(0x20) #define URSEL 7 #define WDTCR _SFR_IO8(0x21) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDTOE 4 #define ASSR _SFR_IO8(0x22) #define TCR2UB 0 #define OCR2UB 1 #define TCN2UB 2 #define AS2 3 #define OCR2 _SFR_IO8(0x23) #define TCNT2 _SFR_IO8(0x24) #define TCCR2 _SFR_IO8(0x25) #define CS20 0 #define CS21 1 #define CS22 2 #define WGM21 3 #define COM20 4 #define COM21 5 #define WGM20 6 #define FOC2 7 /* Combine ICR1L and ICR1H */ #define ICR1 _SFR_IO16(0x26) #define ICR1L _SFR_IO8(0x26) #define ICR1H _SFR_IO8(0x27) /* Combine OCR1BL and OCR1BH */ #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) /* Combine OCR1AL and OCR1AH */ #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) /* Combine TCNT1L and TCNT1H */ #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) #define TCCR1B _SFR_IO8(0x2E) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1A _SFR_IO8(0x2F) #define WGM10 0 #define WGM11 1 #define FOC1B 2 #define FOC1A 3 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 /* The ADHSM bit has been removed from all documentation, as being not needed at all since the comparator has proven to be fast enough even without feeding it more power. */ #define SFIOR _SFR_IO8(0x30) #define PSR10 0 #define PSR2 1 #define PUD 2 #define ACME 3 #define ADTS0 5 #define ADTS1 6 #define ADTS2 7 #define OSCCAL _SFR_IO8(0x31) #define OCDR _SFR_IO8(0x31) #define TCNT0 _SFR_IO8(0x32) #define TCCR0 _SFR_IO8(0x33) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM01 3 #define COM00 4 #define COM01 5 #define WGM00 6 #define FOC0 7 #define MCUCSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define JTRF 4 #define ISC2 6 #define JTD 7 #define MCUCR _SFR_IO8(0x35) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define SM0 4 #define SM1 5 #define SE 6 #define SM2 7 #define TWCR _SFR_IO8(0x36) #define TWIE 0 #define TWEN 2 #define TWWC 3 #define TWSTO 4 #define TWSTA 5 #define TWEA 6 #define TWINT 7 #define SPMCR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define RWWSB 6 #define SPMIE 7 #define TIFR _SFR_IO8(0x38) #define TOV0 0 #define OCF0 1 #define TOV1 2 #define OCF1B 3 #define OCF1A 4 #define ICF1 5 #define TOV2 6 #define OCF2 7 #define TIMSK _SFR_IO8(0x39) #define TOIE0 0 #define OCIE0 1 #define TOIE1 2 #define OCIE1B 3 #define OCIE1A 4 #define TICIE1 5 #define TOIE2 6 #define OCIE2 7 #define GIFR _SFR_IO8(0x3A) #define INTF2 5 #define INTF0 6 #define INTF1 7 #define GICR _SFR_IO8(0x3B) #define IVCE 0 #define IVSEL 1 #define INT2 5 #define INT0 6 #define INT1 7 #define OCR0 _SFR_IO8(0x3C) /* SP [0x3D..0x3E] */ /* SREG [0x3F] */ /* Interrupt vectors */ /* Vector 0 is the reset vector. */ /* External Interrupt Request 0 */ #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt Request 1 */ #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect _VECTOR(3) #define SIG_OUTPUT_COMPARE2 _VECTOR(3) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect _VECTOR(4) #define SIG_OVERFLOW2 _VECTOR(4) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect _VECTOR(5) #define SIG_INPUT_CAPTURE1 _VECTOR(5) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect _VECTOR(6) #define SIG_OUTPUT_COMPARE1A _VECTOR(6) /* Timer/Counter1 Compare Match B */ #define TIMER1_COMPB_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1B _VECTOR(7) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect _VECTOR(8) #define SIG_OVERFLOW1 _VECTOR(8) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect _VECTOR(9) #define SIG_OVERFLOW0 _VECTOR(9) /* Serial Transfer Complete */ #define SPI_STC_vect _VECTOR(10) #define SIG_SPI _VECTOR(10) /* USART, Rx Complete */ #define USART_RXC_vect _VECTOR(11) #define SIG_USART_RECV _VECTOR(11) #define SIG_UART_RECV _VECTOR(11) /* USART Data Register Empty */ #define USART_UDRE_vect _VECTOR(12) #define SIG_USART_DATA _VECTOR(12) #define SIG_UART_DATA _VECTOR(12) /* USART, Tx Complete */ #define USART_TXC_vect _VECTOR(13) #define SIG_USART_TRANS _VECTOR(13) #define SIG_UART_TRANS _VECTOR(13) /* ADC Conversion Complete */ #define ADC_vect _VECTOR(14) #define SIG_ADC _VECTOR(14) /* EEPROM Ready */ #define EE_RDY_vect _VECTOR(15) #define SIG_EEPROM_READY _VECTOR(15) /* Analog Comparator */ #define ANA_COMP_vect _VECTOR(16) #define SIG_COMPARATOR _VECTOR(16) /* 2-wire Serial Interface */ #define TWI_vect _VECTOR(17) #define SIG_2WIRE_SERIAL _VECTOR(17) /* External Interrupt Request 2 */ #define INT2_vect _VECTOR(18) #define SIG_INTERRUPT2 _VECTOR(18) /* Timer/Counter0 Compare Match */ #define TIMER0_COMP_vect _VECTOR(19) #define SIG_OUTPUT_COMPARE0 _VECTOR(19) /* Store Program Memory Ready */ #define SPM_RDY_vect _VECTOR(20) #define SIG_SPM_READY _VECTOR(20) #define _VECTORS_SIZE 84 /* Constants */ #define SPM_PAGESIZE 128 #define RAMEND 0x45F #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x3FFF /* Fuses */ #define FUSE_MEMORY_SIZE 2 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_BODEN (unsigned char)~_BV(6) #define FUSE_BODLEVEL (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_CKOPT (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x03 #endif /* _AVR_IOM16_H_ */

[m16def.inc]	[iom16.h]
;*** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT **************** ;* Created: 2009-11-03 14:40 *** Source: ATmega16.xml ******** ;*********************************************************************** ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y ;* ;* Number : AVR000 ;* File Name : "m16def.inc" ;* Title : Register/Bit Definitions for the ATmega16 ;* Date : 2009-11-03 ;* Version : 2.35 ;* Support E-mail : avr@atmel.com ;* Target MCU : ATmega16 ;* ;* DESCRIPTION ;* When including this file in the assembly program file, all I/O register ;* names and I/O register bit names appearing in the data book can be used. ;* In addition, the six registers forming the three data pointers X, Y and ;* Z have been assigned names XL - ZH. Highest RAM address for Internal ;* SRAM is also defined ;* ;* The Register names are represented by their hexadecimal address. ;* ;* The Register Bit names are represented by their bit number (0-7). ;* ;* Please observe the difference in using the bit names with instructions ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" ;* (skip if bit in register set/cleared). The following example illustrates ;* this: ;* ;* in r16,PORTB ;read PORTB latch ;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) ;* out PORTB,r16 ;output to PORTB ;* ;* in r16,TIFR ;read the Timer Interrupt Flag Register ;* sbrc r16,TOV0 ;test the overflow flag (use bit#) ;* rjmp TOV0_is_set ;jump if set ;* ... ;otherwise do something else ;*********************************************************************** #ifndef _M16DEF_INC_ #define _M16DEF_INC_ #pragma partinc 0 ; * SPECIFY DEVICE *********************************************** .device ATmega16 #pragma AVRPART ADMIN PART_NAME ATmega16 .equ SIGNATURE_000 = 0x1e .equ SIGNATURE_001 = 0x94 .equ SIGNATURE_002 = 0x03 #pragma AVRPART CORE CORE_VERSION V2E ; * I/O REGISTER DEFINITIONS ************************************* ; NOTE: ; Definitions marked "MEMORY MAPPED"are extended I/O ports ; and cannot be used with IN/OUT instructions .equ SREG = 0x3f .equ SPL = 0x3d .equ SPH = 0x3e .equ OCR0 = 0x3c .equ GICR = 0x3b .equ GIFR = 0x3a .equ TIMSK = 0x39 .equ TIFR = 0x38 .equ SPMCSR = 0x37 .equ TWCR = 0x36 .equ MCUCR = 0x35 .equ MCUCSR = 0x34 .equ TCCR0 = 0x33 .equ TCNT0 = 0x32 .equ OSCCAL = 0x31 .equ OCDR = 0x31 .equ SFIOR = 0x30 .equ TCCR1A = 0x2f .equ TCCR1B = 0x2e .equ TCNT1L = 0x2c .equ TCNT1H = 0x2d .equ OCR1AL = 0x2a .equ OCR1AH = 0x2b .equ OCR1BL = 0x28 .equ OCR1BH = 0x29 .equ ICR1L = 0x26 .equ ICR1H = 0x27 .equ TCCR2 = 0x25 .equ TCNT2 = 0x24 .equ OCR2 = 0x23 .equ ASSR = 0x22 .equ WDTCR = 0x21 .equ UBRRH = 0x20 .equ UCSRC = 0x20 .equ EEARL = 0x1e .equ EEARH = 0x1f .equ EEDR = 0x1d .equ EECR = 0x1c .equ PORTA = 0x1b .equ DDRA = 0x1a .equ PINA = 0x19 .equ PORTB = 0x18 .equ DDRB = 0x17 .equ PINB = 0x16 .equ PORTC = 0x15 .equ DDRC = 0x14 .equ PINC = 0x13 .equ PORTD = 0x12 .equ DDRD = 0x11 .equ PIND = 0x10 .equ SPDR = 0x0f .equ SPSR = 0x0e .equ SPCR = 0x0d .equ UDR = 0x0c .equ UCSRA = 0x0b .equ UCSRB = 0x0a .equ UBRRL = 0x09 .equ ACSR = 0x08 .equ ADMUX = 0x07 .equ ADCSRA = 0x06 .equ ADCH = 0x05 .equ ADCL = 0x04 .equ TWDR = 0x03 .equ TWAR = 0x02 .equ TWSR = 0x01 .equ TWBR = 0x00 ; * BIT DEFINITIONS ********************************************** ; * TIMER_COUNTER_0 ********** ; TCCR0 - Timer/Counter Control Register .equ CS00 = 0 ; Clock Select 1 .equ CS01 = 1 ; Clock Select 1 .equ CS02 = 2 ; Clock Select 2 .equ WGM01 = 3 ; Waveform Generation Mode 1 .equ CTC0 = WGM01 ; For compatibility .equ COM00 = 4 ; Compare match Output Mode 0 .equ COM01 = 5 ; Compare Match Output Mode 1 .equ WGM00 = 6 ; Waveform Generation Mode 0 .equ PWM0 = WGM00 ; For compatibility .equ FOC0 = 7 ; Force Output Compare ; TCNT0 - Timer/Counter Register .equ TCNT0_0 = 0 ; .equ TCNT0_1 = 1 ; .equ TCNT0_2 = 2 ; .equ TCNT0_3 = 3 ; .equ TCNT0_4 = 4 ; .equ TCNT0_5 = 5 ; .equ TCNT0_6 = 6 ; .equ TCNT0_7 = 7 ; ; OCR0 - Output Compare Register .equ OCR0_0 = 0 ; .equ OCR0_1 = 1 ; .equ OCR0_2 = 2 ; .equ OCR0_3 = 3 ; .equ OCR0_4 = 4 ; .equ OCR0_5 = 5 ; .equ OCR0_6 = 6 ; .equ OCR0_7 = 7 ; ; TIMSK - Timer/Counter Interrupt Mask Register .equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable .equ OCIE0 = 1 ; Timer/Counter0 Output Compare Match Interrupt register ; TIFR - Timer/Counter Interrupt Flag register .equ TOV0 = 0 ; Timer/Counter0 Overflow Flag .equ OCF0 = 1 ; Output Compare Flag 0 ; SFIOR - Special Function IO Register .equ PSR10 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 ; * TIMER_COUNTER_1 ********** ; TIMSK - Timer/Counter Interrupt Mask Register .equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable .equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable .equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable .equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable ; TIFR - Timer/Counter Interrupt Flag register .equ TOV1 = 2 ; Timer/Counter1 Overflow Flag .equ OCF1B = 3 ; Output Compare Flag 1B .equ OCF1A = 4 ; Output Compare Flag 1A .equ ICF1 = 5 ; Input Capture Flag 1 ; TCCR1A - Timer/Counter1 Control Register A .equ WGM10 = 0 ; Waveform Generation Mode .equ PWM10 = WGM10 ; For compatibility .equ WGM11 = 1 ; Waveform Generation Mode .equ PWM11 = WGM11 ; For compatibility .equ FOC1B = 2 ; Force Output Compare 1B .equ FOC1A = 3 ; Force Output Compare 1A .equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 .equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 .equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0 .equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 ; TCCR1B - Timer/Counter1 Control Register B .equ CS10 = 0 ; Prescaler source of Timer/Counter 1 .equ CS11 = 1 ; Prescaler source of Timer/Counter 1 .equ CS12 = 2 ; Prescaler source of Timer/Counter 1 .equ WGM12 = 3 ; Waveform Generation Mode .equ CTC10 = WGM12 ; For compatibility .equ CTC1 = WGM12 ; For compatibility .equ WGM13 = 4 ; Waveform Generation Mode .equ CTC11 = WGM13 ; For compatibility .equ ICES1 = 6 ; Input Capture 1 Edge Select .equ ICNC1 = 7 ; Input Capture 1 Noise Canceler ; * EXTERNAL_INTERRUPT ******* ; GICR - General Interrupt Control Register .equ GIMSK = GICR ; For compatibility .equ IVCE = 0 ; Interrupt Vector Change Enable .equ IVSEL = 1 ; Interrupt Vector Select .equ INT2 = 5 ; External Interrupt Request 2 Enable .equ INT0 = 6 ; External Interrupt Request 0 Enable .equ INT1 = 7 ; External Interrupt Request 1 Enable ; GIFR - General Interrupt Flag Register .equ INTF2 = 5 ; External Interrupt Flag 2 .equ INTF0 = 6 ; External Interrupt Flag 0 .equ INTF1 = 7 ; External Interrupt Flag 1 ; MCUCR - General Interrupt Control Register .equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 .equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 .equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 .equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 ; MCUCSR - MCU Control And Status Register .equ ISC2 = 6 ; Interrupt Sense Control 2 ; * EEPROM ******************* ; EEDR - EEPROM Data Register .equ EEDR0 = 0 ; EEPROM Data Register bit 0 .equ EEDR1 = 1 ; EEPROM Data Register bit 1 .equ EEDR2 = 2 ; EEPROM Data Register bit 2 .equ EEDR3 = 3 ; EEPROM Data Register bit 3 .equ EEDR4 = 4 ; EEPROM Data Register bit 4 .equ EEDR5 = 5 ; EEPROM Data Register bit 5 .equ EEDR6 = 6 ; EEPROM Data Register bit 6 .equ EEDR7 = 7 ; EEPROM Data Register bit 7 ; EECR - EEPROM Control Register .equ EERE = 0 ; EEPROM Read Enable .equ EEWE = 1 ; EEPROM Write Enable .equ EEMWE = 2 ; EEPROM Master Write Enable .equ EEWEE = EEMWE ; For compatibility .equ EERIE = 3 ; EEPROM Ready Interrupt Enable ; * CPU ********************** ; SREG - Status Register .equ SREG_C = 0 ; Carry Flag .equ SREG_Z = 1 ; Zero Flag .equ SREG_N = 2 ; Negative Flag .equ SREG_V = 3 ; Two's Complement Overflow Flag .equ SREG_S = 4 ; Sign Bit .equ SREG_H = 5 ; Half Carry Flag .equ SREG_T = 6 ; Bit Copy Storage .equ SREG_I = 7 ; Global Interrupt Enable ; MCUCR - MCU Control Register ;.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 ;.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 ;.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 ;.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 .equ SM0 = 4 ; Sleep Mode Select .equ SM1 = 5 ; Sleep Mode Select .equ SE = 6 ; Sleep Enable .equ SM2 = 7 ; Sleep Mode Select ; MCUCSR - MCU Control And Status Register .equ MCUSR = MCUCSR ; For compatibility .equ PORF = 0 ; Power-on reset flag .equ EXTRF = 1 ; External Reset Flag .equ EXTREF = EXTRF ; For compatibility .equ BORF = 2 ; Brown-out Reset Flag .equ WDRF = 3 ; Watchdog Reset Flag .equ JTRF = 4 ; JTAG Reset Flag .equ JTD = 7 ; JTAG Interface Disable ; OSCCAL - Oscillator Calibration Value .equ CAL0 = 0 ; Oscillator Calibration Value Bit0 .equ CAL1 = 1 ; Oscillator Calibration Value Bit1 .equ CAL2 = 2 ; Oscillator Calibration Value Bit2 .equ CAL3 = 3 ; Oscillator Calibration Value Bit3 .equ CAL4 = 4 ; Oscillator Calibration Value Bit4 .equ CAL5 = 5 ; Oscillator Calibration Value Bit5 .equ CAL6 = 6 ; Oscillator Calibration Value Bit6 .equ CAL7 = 7 ; Oscillator Calibration Value Bit7 ; SFIOR - Special function I/O register ;.equ PSR10 = 0 ; Prescaler reset .equ PSR2 = 1 ; Prescaler reset .equ PUD = 2 ; Pull-up Disable ; * TIMER_COUNTER_2 ********** ; TIMSK - Timer/Counter Interrupt Mask register .equ TOIE2 = 6 ; Timer/Counter2 Overflow Interrupt Enable .equ OCIE2 = 7 ; Timer/Counter2 Output Compare Match Interrupt Enable ; TIFR - Timer/Counter Interrupt Flag Register .equ TOV2 = 6 ; Timer/Counter2 Overflow Flag .equ OCF2 = 7 ; Output Compare Flag 2 ; TCCR2 - Timer/Counter2 Control Register .equ CS20 = 0 ; Clock Select bit 0 .equ CS21 = 1 ; Clock Select bit 1 .equ CS22 = 2 ; Clock Select bit 2 .equ WGM21 = 3 ; Waveform Generation Mode .equ CTC2 = WGM21 ; For compatibility .equ COM20 = 4 ; Compare Output Mode bit 0 .equ COM21 = 5 ; Compare Output Mode bit 1 .equ WGM20 = 6 ; Waveform Genration Mode .equ PWM2 = WGM20 ; For compatibility .equ FOC2 = 7 ; Force Output Compare ; TCNT2 - Timer/Counter2 .equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 .equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 .equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 .equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 .equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 .equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 .equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 .equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 ; OCR2 - Timer/Counter2 Output Compare Register .equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 .equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 .equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 .equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 .equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 .equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 .equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 .equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 ; ASSR - Asynchronous Status Register .equ TCR2UB = 0 ; Timer/counter Control Register2 Update Busy .equ OCR2UB = 1 ; Output Compare Register2 Update Busy .equ TCN2UB = 2 ; Timer/Counter2 Update Busy .equ AS2 = 3 ; Asynchronous Timer/counter2 ; SFIOR - Special Function IO Register ;.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 ; * SPI ********************** ; SPDR - SPI Data Register .equ SPDR0 = 0 ; SPI Data Register bit 0 .equ SPDR1 = 1 ; SPI Data Register bit 1 .equ SPDR2 = 2 ; SPI Data Register bit 2 .equ SPDR3 = 3 ; SPI Data Register bit 3 .equ SPDR4 = 4 ; SPI Data Register bit 4 .equ SPDR5 = 5 ; SPI Data Register bit 5 .equ SPDR6 = 6 ; SPI Data Register bit 6 .equ SPDR7 = 7 ; SPI Data Register bit 7 ; SPSR - SPI Status Register .equ SPI2X = 0 ; Double SPI Speed Bit .equ WCOL = 6 ; Write Collision Flag .equ SPIF = 7 ; SPI Interrupt Flag ; SPCR - SPI Control Register .equ SPR0 = 0 ; SPI Clock Rate Select 0 .equ SPR1 = 1 ; SPI Clock Rate Select 1 .equ CPHA = 2 ; Clock Phase .equ CPOL = 3 ; Clock polarity .equ MSTR = 4 ; Master/Slave Select .equ DORD = 5 ; Data Order .equ SPE = 6 ; SPI Enable .equ SPIE = 7 ; SPI Interrupt Enable ; * USART ******************** ; UDR - USART I/O Data Register .equ UDR0 = 0 ; USART I/O Data Register bit 0 .equ UDR1 = 1 ; USART I/O Data Register bit 1 .equ UDR2 = 2 ; USART I/O Data Register bit 2 .equ UDR3 = 3 ; USART I/O Data Register bit 3 .equ UDR4 = 4 ; USART I/O Data Register bit 4 .equ UDR5 = 5 ; USART I/O Data Register bit 5 .equ UDR6 = 6 ; USART I/O Data Register bit 6 .equ UDR7 = 7 ; USART I/O Data Register bit 7 ; UCSRA - USART Control and Status Register A .equ USR = UCSRA ; For compatibility .equ MPCM = 0 ; Multi-processor Communication Mode .equ U2X = 1 ; Double the USART transmission speed .equ UPE = 2 ; Parity Error .equ PE = UPE ; For compatibility .equ DOR = 3 ; Data overRun .equ FE = 4 ; Framing Error .equ UDRE = 5 ; USART Data Register Empty .equ TXC = 6 ; USART Transmitt Complete .equ RXC = 7 ; USART Receive Complete ; UCSRB - USART Control and Status Register B .equ UCR = UCSRB ; For compatibility .equ TXB8 = 0 ; Transmit Data Bit 8 .equ RXB8 = 1 ; Receive Data Bit 8 .equ UCSZ2 = 2 ; Character Size .equ CHR9 = UCSZ2 ; For compatibility .equ TXEN = 3 ; Transmitter Enable .equ RXEN = 4 ; Receiver Enable .equ UDRIE = 5 ; USART Data register Empty Interrupt Enable .equ TXCIE = 6 ; TX Complete Interrupt Enable .equ RXCIE = 7 ; RX Complete Interrupt Enable ; UCSRC - USART Control and Status Register C .equ UCPOL = 0 ; Clock Polarity .equ UCSZ0 = 1 ; Character Size .equ UCSZ1 = 2 ; Character Size .equ USBS = 3 ; Stop Bit Select .equ UPM0 = 4 ; Parity Mode Bit 0 .equ UPM1 = 5 ; Parity Mode Bit 1 .equ UMSEL = 6 ; USART Mode Select .equ URSEL = 7 ; Register Select .equ UBRRHI = UBRRH ; For compatibility ; * TWI ********************** ; TWBR - TWI Bit Rate register .equ I2BR = TWBR ; For compatibility .equ TWBR0 = 0 ; .equ TWBR1 = 1 ; .equ TWBR2 = 2 ; .equ TWBR3 = 3 ; .equ TWBR4 = 4 ; .equ TWBR5 = 5 ; .equ TWBR6 = 6 ; .equ TWBR7 = 7 ; ; TWCR - TWI Control Register .equ I2CR = TWCR ; For compatibility .equ TWIE = 0 ; TWI Interrupt Enable .equ I2IE = TWIE ; For compatibility .equ TWEN = 2 ; TWI Enable Bit .equ I2EN = TWEN ; For compatibility .equ ENI2C = TWEN ; For compatibility .equ TWWC = 3 ; TWI Write Collition Flag .equ I2WC = TWWC ; For compatibility .equ TWSTO = 4 ; TWI Stop Condition Bit .equ I2STO = TWSTO ; For compatibility .equ TWSTA = 5 ; TWI Start Condition Bit .equ I2STA = TWSTA ; For compatibility .equ TWEA = 6 ; TWI Enable Acknowledge Bit .equ I2EA = TWEA ; For compatibility .equ TWINT = 7 ; TWI Interrupt Flag .equ I2INT = TWINT ; For compatibility ; TWSR - TWI Status Register .equ I2SR = TWSR ; For compatibility .equ TWPS0 = 0 ; TWI Prescaler .equ TWS0 = TWPS0 ; For compatibility .equ I2GCE = TWPS0 ; For compatibility .equ TWPS1 = 1 ; TWI Prescaler .equ TWS1 = TWPS1 ; For compatibility .equ TWS3 = 3 ; TWI Status .equ I2S3 = TWS3 ; For compatibility .equ TWS4 = 4 ; TWI Status .equ I2S4 = TWS4 ; For compatibility .equ TWS5 = 5 ; TWI Status .equ I2S5 = TWS5 ; For compatibility .equ TWS6 = 6 ; TWI Status .equ I2S6 = TWS6 ; For compatibility .equ TWS7 = 7 ; TWI Status .equ I2S7 = TWS7 ; For compatibility ; TWDR - TWI Data register .equ I2DR = TWDR ; For compatibility .equ TWD0 = 0 ; TWI Data Register Bit 0 .equ TWD1 = 1 ; TWI Data Register Bit 1 .equ TWD2 = 2 ; TWI Data Register Bit 2 .equ TWD3 = 3 ; TWI Data Register Bit 3 .equ TWD4 = 4 ; TWI Data Register Bit 4 .equ TWD5 = 5 ; TWI Data Register Bit 5 .equ TWD6 = 6 ; TWI Data Register Bit 6 .equ TWD7 = 7 ; TWI Data Register Bit 7 ; TWAR - TWI (Slave) Address register .equ I2AR = TWAR ; For compatibility .equ TWGCE = 0 ; TWI General Call Recognition Enable Bit .equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 .equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 .equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 .equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 .equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 .equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 .equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 ; * ANALOG_COMPARATOR ******** ; SFIOR - Special Function IO Register .equ ACME = 3 ; Analog Comparator Multiplexer Enable ; ACSR - Analog Comparator Control And Status Register .equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 .equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 .equ ACIC = 2 ; Analog Comparator Input Capture Enable .equ ACIE = 3 ; Analog Comparator Interrupt Enable .equ ACI = 4 ; Analog Comparator Interrupt Flag .equ ACO = 5 ; Analog Compare Output .equ ACBG = 6 ; Analog Comparator Bandgap Select .equ ACD = 7 ; Analog Comparator Disable ; * AD_CONVERTER ************* ; ADMUX - The ADC multiplexer Selection Register .equ MUX0 = 0 ; Analog Channel and Gain Selection Bits .equ MUX1 = 1 ; Analog Channel and Gain Selection Bits .equ MUX2 = 2 ; Analog Channel and Gain Selection Bits .equ MUX3 = 3 ; Analog Channel and Gain Selection Bits .equ MUX4 = 4 ; Analog Channel and Gain Selection Bits .equ ADLAR = 5 ; Left Adjust Result .equ REFS0 = 6 ; Reference Selection Bit 0 .equ REFS1 = 7 ; Reference Selection Bit 1 ; ADCSRA - The ADC Control and Status register .equ ADCSR = ADCSRA ; For compatibility .equ ADPS0 = 0 ; ADC Prescaler Select Bits .equ ADPS1 = 1 ; ADC Prescaler Select Bits .equ ADPS2 = 2 ; ADC Prescaler Select Bits .equ ADIE = 3 ; ADC Interrupt Enable .equ ADIF = 4 ; ADC Interrupt Flag .equ ADATE = 5 ; When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset. .equ ADFR = ADATE ; For compatibility .equ ADSC = 6 ; ADC Start Conversion .equ ADEN = 7 ; ADC Enable ; ADCH - ADC Data Register High Byte .equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 .equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 .equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 .equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 .equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 .equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 .equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 .equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 ; ADCL - ADC Data Register Low Byte .equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 .equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 .equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 .equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 .equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 .equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 .equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 .equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 ; SFIOR - Special Function IO Register .equ ADTS0 = 5 ; ADC Auto Trigger Source 0 .equ ADTS1 = 6 ; ADC Auto Trigger Source 1 .equ ADTS2 = 7 ; ADC Auto Trigger Source 2 ; * JTAG ********************* ; OCDR - On-Chip Debug Related Register in I/O Memory .equ OCDR0 = 0 ; On-Chip Debug Register Bit 0 .equ OCDR1 = 1 ; On-Chip Debug Register Bit 1 .equ OCDR2 = 2 ; On-Chip Debug Register Bit 2 .equ OCDR3 = 3 ; On-Chip Debug Register Bit 3 .equ OCDR4 = 4 ; On-Chip Debug Register Bit 4 .equ OCDR5 = 5 ; On-Chip Debug Register Bit 5 .equ OCDR6 = 6 ; On-Chip Debug Register Bit 6 .equ OCDR7 = 7 ; On-Chip Debug Register Bit 7 .equ IDRD = OCDR7 ; For compatibility ; MCUCSR - MCU Control And Status Register ;.equ JTRF = 4 ; JTAG Reset Flag ;.equ JTD = 7 ; JTAG Interface Disable ; * BOOT_LOAD **************** ; SPMCSR - Store Program Memory Control Register .equ SPMCR = SPMCSR ; For compatibility .equ SPMEN = 0 ; Store Program Memory Enable .equ PGERS = 1 ; Page Erase .equ PGWRT = 2 ; Page Write .equ BLBSET = 3 ; Boot Lock Bit Set .equ RWWSRE = 4 ; Read While Write section read enable .equ ASRE = RWWSRE ; For compatibility .equ RWWSB = 6 ; Read While Write Section Busy .equ ASB = RWWSB ; For compatibility .equ SPMIE = 7 ; SPM Interrupt Enable ; * PORTA ******************** ; PORTA - Port A Data Register .equ PORTA0 = 0 ; Port A Data Register bit 0 .equ PA0 = 0 ; For compatibility .equ PORTA1 = 1 ; Port A Data Register bit 1 .equ PA1 = 1 ; For compatibility .equ PORTA2 = 2 ; Port A Data Register bit 2 .equ PA2 = 2 ; For compatibility .equ PORTA3 = 3 ; Port A Data Register bit 3 .equ PA3 = 3 ; For compatibility .equ PORTA4 = 4 ; Port A Data Register bit 4 .equ PA4 = 4 ; For compatibility .equ PORTA5 = 5 ; Port A Data Register bit 5 .equ PA5 = 5 ; For compatibility .equ PORTA6 = 6 ; Port A Data Register bit 6 .equ PA6 = 6 ; For compatibility .equ PORTA7 = 7 ; Port A Data Register bit 7 .equ PA7 = 7 ; For compatibility ; DDRA - Port A Data Direction Register .equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 .equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 .equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 .equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 .equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 .equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 .equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 .equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 ; PINA - Port A Input Pins .equ PINA0 = 0 ; Input Pins, Port A bit 0 .equ PINA1 = 1 ; Input Pins, Port A bit 1 .equ PINA2 = 2 ; Input Pins, Port A bit 2 .equ PINA3 = 3 ; Input Pins, Port A bit 3 .equ PINA4 = 4 ; Input Pins, Port A bit 4 .equ PINA5 = 5 ; Input Pins, Port A bit 5 .equ PINA6 = 6 ; Input Pins, Port A bit 6 .equ PINA7 = 7 ; Input Pins, Port A bit 7 ; * PORTB ******************** ; PORTB - Port B Data Register .equ PORTB0 = 0 ; Port B Data Register bit 0 .equ PB0 = 0 ; For compatibility .equ PORTB1 = 1 ; Port B Data Register bit 1 .equ PB1 = 1 ; For compatibility .equ PORTB2 = 2 ; Port B Data Register bit 2 .equ PB2 = 2 ; For compatibility .equ PORTB3 = 3 ; Port B Data Register bit 3 .equ PB3 = 3 ; For compatibility .equ PORTB4 = 4 ; Port B Data Register bit 4 .equ PB4 = 4 ; For compatibility .equ PORTB5 = 5 ; Port B Data Register bit 5 .equ PB5 = 5 ; For compatibility .equ PORTB6 = 6 ; Port B Data Register bit 6 .equ PB6 = 6 ; For compatibility .equ PORTB7 = 7 ; Port B Data Register bit 7 .equ PB7 = 7 ; For compatibility ; DDRB - Port B Data Direction Register .equ DDB0 = 0 ; Port B Data Direction Register bit 0 .equ DDB1 = 1 ; Port B Data Direction Register bit 1 .equ DDB2 = 2 ; Port B Data Direction Register bit 2 .equ DDB3 = 3 ; Port B Data Direction Register bit 3 .equ DDB4 = 4 ; Port B Data Direction Register bit 4 .equ DDB5 = 5 ; Port B Data Direction Register bit 5 .equ DDB6 = 6 ; Port B Data Direction Register bit 6 .equ DDB7 = 7 ; Port B Data Direction Register bit 7 ; PINB - Port B Input Pins .equ PINB0 = 0 ; Port B Input Pins bit 0 .equ PINB1 = 1 ; Port B Input Pins bit 1 .equ PINB2 = 2 ; Port B Input Pins bit 2 .equ PINB3 = 3 ; Port B Input Pins bit 3 .equ PINB4 = 4 ; Port B Input Pins bit 4 .equ PINB5 = 5 ; Port B Input Pins bit 5 .equ PINB6 = 6 ; Port B Input Pins bit 6 .equ PINB7 = 7 ; Port B Input Pins bit 7 ; * PORTC ******************** ; PORTC - Port C Data Register .equ PORTC0 = 0 ; Port C Data Register bit 0 .equ PC0 = 0 ; For compatibility .equ PORTC1 = 1 ; Port C Data Register bit 1 .equ PC1 = 1 ; For compatibility .equ PORTC2 = 2 ; Port C Data Register bit 2 .equ PC2 = 2 ; For compatibility .equ PORTC3 = 3 ; Port C Data Register bit 3 .equ PC3 = 3 ; For compatibility .equ PORTC4 = 4 ; Port C Data Register bit 4 .equ PC4 = 4 ; For compatibility .equ PORTC5 = 5 ; Port C Data Register bit 5 .equ PC5 = 5 ; For compatibility .equ PORTC6 = 6 ; Port C Data Register bit 6 .equ PC6 = 6 ; For compatibility .equ PORTC7 = 7 ; Port C Data Register bit 7 .equ PC7 = 7 ; For compatibility ; DDRC - Port C Data Direction Register .equ DDC0 = 0 ; Port C Data Direction Register bit 0 .equ DDC1 = 1 ; Port C Data Direction Register bit 1 .equ DDC2 = 2 ; Port C Data Direction Register bit 2 .equ DDC3 = 3 ; Port C Data Direction Register bit 3 .equ DDC4 = 4 ; Port C Data Direction Register bit 4 .equ DDC5 = 5 ; Port C Data Direction Register bit 5 .equ DDC6 = 6 ; Port C Data Direction Register bit 6 .equ DDC7 = 7 ; Port C Data Direction Register bit 7 ; PINC - Port C Input Pins .equ PINC0 = 0 ; Port C Input Pins bit 0 .equ PINC1 = 1 ; Port C Input Pins bit 1 .equ PINC2 = 2 ; Port C Input Pins bit 2 .equ PINC3 = 3 ; Port C Input Pins bit 3 .equ PINC4 = 4 ; Port C Input Pins bit 4 .equ PINC5 = 5 ; Port C Input Pins bit 5 .equ PINC6 = 6 ; Port C Input Pins bit 6 .equ PINC7 = 7 ; Port C Input Pins bit 7 ; * PORTD ******************** ; PORTD - Port D Data Register .equ PORTD0 = 0 ; Port D Data Register bit 0 .equ PD0 = 0 ; For compatibility .equ PORTD1 = 1 ; Port D Data Register bit 1 .equ PD1 = 1 ; For compatibility .equ PORTD2 = 2 ; Port D Data Register bit 2 .equ PD2 = 2 ; For compatibility .equ PORTD3 = 3 ; Port D Data Register bit 3 .equ PD3 = 3 ; For compatibility .equ PORTD4 = 4 ; Port D Data Register bit 4 .equ PD4 = 4 ; For compatibility .equ PORTD5 = 5 ; Port D Data Register bit 5 .equ PD5 = 5 ; For compatibility .equ PORTD6 = 6 ; Port D Data Register bit 6 .equ PD6 = 6 ; For compatibility .equ PORTD7 = 7 ; Port D Data Register bit 7 .equ PD7 = 7 ; For compatibility ; DDRD - Port D Data Direction Register .equ DDD0 = 0 ; Port D Data Direction Register bit 0 .equ DDD1 = 1 ; Port D Data Direction Register bit 1 .equ DDD2 = 2 ; Port D Data Direction Register bit 2 .equ DDD3 = 3 ; Port D Data Direction Register bit 3 .equ DDD4 = 4 ; Port D Data Direction Register bit 4 .equ DDD5 = 5 ; Port D Data Direction Register bit 5 .equ DDD6 = 6 ; Port D Data Direction Register bit 6 .equ DDD7 = 7 ; Port D Data Direction Register bit 7 ; PIND - Port D Input Pins .equ PIND0 = 0 ; Port D Input Pins bit 0 .equ PIND1 = 1 ; Port D Input Pins bit 1 .equ PIND2 = 2 ; Port D Input Pins bit 2 .equ PIND3 = 3 ; Port D Input Pins bit 3 .equ PIND4 = 4 ; Port D Input Pins bit 4 .equ PIND5 = 5 ; Port D Input Pins bit 5 .equ PIND6 = 6 ; Port D Input Pins bit 6 .equ PIND7 = 7 ; Port D Input Pins bit 7 ; * WATCHDOG ***************** ; WDTCR - Watchdog Timer Control Register .equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 .equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 .equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 .equ WDE = 3 ; Watch Dog Enable .equ WDTOE = 4 ; RW .equ WDDE = WDTOE ; For compatibility ; * LOCKSBITS **************************************************** .equ LB1 = 0 ; Lock bit .equ LB2 = 1 ; Lock bit .equ BLB01 = 2 ; Boot Lock bit .equ BLB02 = 3 ; Boot Lock bit .equ BLB11 = 4 ; Boot lock bit .equ BLB12 = 5 ; Boot lock bit ; * FUSES ******************************************************** ; LOW fuse bits .equ CKSEL0 = 0 ; Select Clock Source .equ CKSEL1 = 1 ; Select Clock Source .equ CKSEL2 = 2 ; Select Clock Source .equ CKSEL3 = 3 ; Select Clock Source .equ SUT0 = 4 ; Select start-up time .equ SUT1 = 5 ; Select start-up time .equ BODEN = 6 ; Brown out detector enable .equ BODLEVEL = 7 ; Brown out detector trigger level ; HIGH fuse bits .equ BOOTRST = 0 ; Select Reset Vector .equ BOOTSZ0 = 1 ; Select Boot Size .equ BOOTSZ1 = 2 ; Select Boot Size .equ EESAVE = 3 ; EEPROM memory is preserved through chip erase .equ CKOPT = 4 ; Oscillator Options .equ SPIEN = 5 ; Enable Serial programming and Data Downloading .equ JTAGEN = 6 ; Enable JTAG .equ OCDEN = 7 ; Enable OCD ; * CPU REGISTER DEFINITIONS ************************************* .def XH = r27 .def XL = r26 .def YH = r29 .def YL = r28 .def ZH = r31 .def ZL = r30 ; * DATA MEMORY DECLARATIONS ************************************* .equ FLASHEND = 0x1fff ; Note: Word address .equ IOEND = 0x003f .equ SRAM_START = 0x0060 .equ SRAM_SIZE = 1024 .equ RAMEND = 0x045f .equ XRAMEND = 0x0000 .equ E2END = 0x01ff .equ EEPROMEND = 0x01ff .equ EEADRBITS = 9 #pragma AVRPART MEMORY PROG_FLASH 16384 #pragma AVRPART MEMORY EEPROM 512 #pragma AVRPART MEMORY INT_SRAM SIZE 1024 #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 ; * BOOTLOADER DECLARATIONS ************************************** .equ NRWW_START_ADDR = 0x1c00 .equ NRWW_STOP_ADDR = 0x1fff .equ RWW_START_ADDR = 0x0 .equ RWW_STOP_ADDR = 0x1bff .equ PAGESIZE = 64 .equ FIRSTBOOTSTART = 0x1f80 .equ SECONDBOOTSTART = 0x1f00 .equ THIRDBOOTSTART = 0x1e00 .equ FOURTHBOOTSTART = 0x1c00 .equ SMALLBOOTSTART = FIRSTBOOTSTART .equ LARGEBOOTSTART = FOURTHBOOTSTART ; * INTERRUPT VECTORS ********************************************** .equ INT0addr = 0x0002 ; External Interrupt Request 0 .equ INT1addr = 0x0004 ; External Interrupt Request 1 .equ OC2addr = 0x0006 ; Timer/Counter2 Compare Match .equ OVF2addr = 0x0008 ; Timer/Counter2 Overflow .equ ICP1addr = 0x000a ; Timer/Counter1 Capture Event .equ OC1Aaddr = 0x000c ; Timer/Counter1 Compare Match A .equ OC1Baddr = 0x000e ; Timer/Counter1 Compare Match B .equ OVF1addr = 0x0010 ; Timer/Counter1 Overflow .equ OVF0addr = 0x0012 ; Timer/Counter0 Overflow .equ SPIaddr = 0x0014 ; Serial Transfer Complete .equ URXCaddr = 0x0016 ; USART, Rx Complete .equ UDREaddr = 0x0018 ; USART Data Register Empty .equ UTXCaddr = 0x001a ; USART, Tx Complete .equ ADCCaddr = 0x001c ; ADC Conversion Complete .equ ERDYaddr = 0x001e ; EEPROM Ready .equ ACIaddr = 0x0020 ; Analog Comparator .equ TWIaddr = 0x0022 ; 2-wire Serial Interface .equ INT2addr = 0x0024 ; External Interrupt Request 2 .equ OC0addr = 0x0026 ; Timer/Counter0 Compare Match .equ SPMRaddr = 0x0028 ; Store Program Memory Ready .equ INT_VECTORS_SIZE = 42 ; size in words #endif /* _M16DEF_INC_ / ; ** END OF FILE ****************************************************	/* Copyright (c) 2004 Eric B. Weddington All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. / / $Id: iom16.h,v 1.14.2.6 2009/02/11 18:05:26 arcanum Exp $ / / avr/iom16.h - definitions for ATmega16 / #ifndef _AVR_IOM16_H_ #define _AVR_IOM16_H_ 1 / This file should only be included from <avr/io.h>, never directly. / #ifndef _AVR_IO_H_ # error "Include <avr/io.h> instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom16.h" #else # error "Attempt to include more than one <avr/ioXXX.h> file." #endif / Registers and associated bit numbers / #define TWBR _SFR_IO8(0x00) #define TWSR _SFR_IO8(0x01) #define TWPS0 0 #define TWPS1 1 #define TWS3 3 #define TWS4 4 #define TWS5 5 #define TWS6 6 #define TWS7 7 #define TWAR _SFR_IO8(0x02) #define TWGCE 0 #define TWA0 1 #define TWA1 2 #define TWA2 3 #define TWA3 4 #define TWA4 5 #define TWA5 6 #define TWA6 7 #define TWDR _SFR_IO8(0x03) / Combine ADCL and ADCH / #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCW _SFR_IO16(0x04) #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) #define ADCSRA _SFR_IO8(0x06) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADMUX _SFR_IO8(0x07) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define ACSR _SFR_IO8(0x08) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define UBRRL _SFR_IO8(0x09) #define UCSRB _SFR_IO8(0x0A) #define TXB8 0 #define RXB8 1 #define UCSZ2 2 #define TXEN 3 #define RXEN 4 #define UDRIE 5 #define TXCIE 6 #define RXCIE 7 #define UCSRA _SFR_IO8(0x0B) #define MPCM 0 #define U2X 1 #define PE 2 #define DOR 3 #define FE 4 #define UDRE 5 #define TXC 6 #define RXC 7 #define UDR _SFR_IO8(0x0C) #define SPCR _SFR_IO8(0x0D) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x0E) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x0F) #define PIND _SFR_IO8(0x10) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x11) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x12) #define PD0 0 #define PD1 1 #define PD2 2 #define PD3 3 #define PD4 4 #define PD5 5 #define PD6 6 #define PD7 7 #define PINC _SFR_IO8(0x13) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define PINC7 7 #define DDRC _SFR_IO8(0x14) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define DDC7 7 #define PORTC _SFR_IO8(0x15) #define PC0 0 #define PC1 1 #define PC2 2 #define PC3 3 #define PC4 4 #define PC5 5 #define PC6 6 #define PC7 7 #define PINB _SFR_IO8(0x16) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x17) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x18) #define PB0 0 #define PB1 1 #define PB2 2 #define PB3 3 #define PB4 4 #define PB5 5 #define PB6 6 #define PB7 7 #define PINA _SFR_IO8(0x19) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define PINA4 4 #define PINA5 5 #define PINA6 6 #define PINA7 7 #define DDRA _SFR_IO8(0x1A) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define DDA4 4 #define DDA5 5 #define DDA6 6 #define DDA7 7 #define PORTA _SFR_IO8(0x1B) #define PA0 0 #define PA1 1 #define PA2 2 #define PA3 3 #define PA4 4 #define PA5 5 #define PA6 6 #define PA7 7 / EEPROM Control Register / #define EECR _SFR_IO8(0x1C) #define EERE 0 #define EEWE 1 #define EEMWE 2 #define EERIE 3 / EEPROM Data Register / #define EEDR _SFR_IO8(0x1D) / EEPROM Address Register / #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEARH _SFR_IO8(0x1F) #define UCSRC _SFR_IO8(0x20) #define UCPOL 0 #define UCSZ0 1 #define UCSZ1 2 #define USBS 3 #define UPM0 4 #define UPM1 5 #define UMSEL 6 #define URSEL 7 #define UBRRH _SFR_IO8(0x20) #define URSEL 7 #define WDTCR _SFR_IO8(0x21) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDTOE 4 #define ASSR _SFR_IO8(0x22) #define TCR2UB 0 #define OCR2UB 1 #define TCN2UB 2 #define AS2 3 #define OCR2 _SFR_IO8(0x23) #define TCNT2 _SFR_IO8(0x24) #define TCCR2 _SFR_IO8(0x25) #define CS20 0 #define CS21 1 #define CS22 2 #define WGM21 3 #define COM20 4 #define COM21 5 #define WGM20 6 #define FOC2 7 / Combine ICR1L and ICR1H / #define ICR1 _SFR_IO16(0x26) #define ICR1L _SFR_IO8(0x26) #define ICR1H _SFR_IO8(0x27) / Combine OCR1BL and OCR1BH / #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) / Combine OCR1AL and OCR1AH / #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) / Combine TCNT1L and TCNT1H / #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) #define TCCR1B _SFR_IO8(0x2E) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1A _SFR_IO8(0x2F) #define WGM10 0 #define WGM11 1 #define FOC1B 2 #define FOC1A 3 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 / The ADHSM bit has been removed from all documentation, as being not needed at all since the comparator has proven to be fast enough even without feeding it more power. / #define SFIOR _SFR_IO8(0x30) #define PSR10 0 #define PSR2 1 #define PUD 2 #define ACME 3 #define ADTS0 5 #define ADTS1 6 #define ADTS2 7 #define OSCCAL _SFR_IO8(0x31) #define OCDR _SFR_IO8(0x31) #define TCNT0 _SFR_IO8(0x32) #define TCCR0 _SFR_IO8(0x33) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM01 3 #define COM00 4 #define COM01 5 #define WGM00 6 #define FOC0 7 #define MCUCSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define JTRF 4 #define ISC2 6 #define JTD 7 #define MCUCR _SFR_IO8(0x35) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define SM0 4 #define SM1 5 #define SE 6 #define SM2 7 #define TWCR _SFR_IO8(0x36) #define TWIE 0 #define TWEN 2 #define TWWC 3 #define TWSTO 4 #define TWSTA 5 #define TWEA 6 #define TWINT 7 #define SPMCR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define RWWSB 6 #define SPMIE 7 #define TIFR _SFR_IO8(0x38) #define TOV0 0 #define OCF0 1 #define TOV1 2 #define OCF1B 3 #define OCF1A 4 #define ICF1 5 #define TOV2 6 #define OCF2 7 #define TIMSK _SFR_IO8(0x39) #define TOIE0 0 #define OCIE0 1 #define TOIE1 2 #define OCIE1B 3 #define OCIE1A 4 #define TICIE1 5 #define TOIE2 6 #define OCIE2 7 #define GIFR _SFR_IO8(0x3A) #define INTF2 5 #define INTF0 6 #define INTF1 7 #define GICR _SFR_IO8(0x3B) #define IVCE 0 #define IVSEL 1 #define INT2 5 #define INT0 6 #define INT1 7 #define OCR0 _SFR_IO8(0x3C) / SP [0x3D..0x3E] / / SREG [0x3F] / / Interrupt vectors / / Vector 0 is the reset vector. / / External Interrupt Request 0 / #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) / External Interrupt Request 1 / #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) / Timer/Counter2 Compare Match / #define TIMER2_COMP_vect _VECTOR(3) #define SIG_OUTPUT_COMPARE2 _VECTOR(3) / Timer/Counter2 Overflow / #define TIMER2_OVF_vect _VECTOR(4) #define SIG_OVERFLOW2 _VECTOR(4) / Timer/Counter1 Capture Event / #define TIMER1_CAPT_vect _VECTOR(5) #define SIG_INPUT_CAPTURE1 _VECTOR(5) / Timer/Counter1 Compare Match A / #define TIMER1_COMPA_vect _VECTOR(6) #define SIG_OUTPUT_COMPARE1A _VECTOR(6) / Timer/Counter1 Compare Match B / #define TIMER1_COMPB_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1B _VECTOR(7) / Timer/Counter1 Overflow / #define TIMER1_OVF_vect _VECTOR(8) #define SIG_OVERFLOW1 _VECTOR(8) / Timer/Counter0 Overflow / #define TIMER0_OVF_vect _VECTOR(9) #define SIG_OVERFLOW0 _VECTOR(9) / Serial Transfer Complete / #define SPI_STC_vect _VECTOR(10) #define SIG_SPI _VECTOR(10) / USART, Rx Complete / #define USART_RXC_vect _VECTOR(11) #define SIG_USART_RECV _VECTOR(11) #define SIG_UART_RECV _VECTOR(11) / USART Data Register Empty / #define USART_UDRE_vect _VECTOR(12) #define SIG_USART_DATA _VECTOR(12) #define SIG_UART_DATA _VECTOR(12) / USART, Tx Complete / #define USART_TXC_vect _VECTOR(13) #define SIG_USART_TRANS _VECTOR(13) #define SIG_UART_TRANS _VECTOR(13) / ADC Conversion Complete / #define ADC_vect _VECTOR(14) #define SIG_ADC _VECTOR(14) / EEPROM Ready / #define EE_RDY_vect _VECTOR(15) #define SIG_EEPROM_READY _VECTOR(15) / Analog Comparator / #define ANA_COMP_vect _VECTOR(16) #define SIG_COMPARATOR _VECTOR(16) / 2-wire Serial Interface / #define TWI_vect _VECTOR(17) #define SIG_2WIRE_SERIAL _VECTOR(17) / External Interrupt Request 2 / #define INT2_vect _VECTOR(18) #define SIG_INTERRUPT2 _VECTOR(18) / Timer/Counter0 Compare Match / #define TIMER0_COMP_vect _VECTOR(19) #define SIG_OUTPUT_COMPARE0 _VECTOR(19) / Store Program Memory Ready / #define SPM_RDY_vect _VECTOR(20) #define SIG_SPM_READY _VECTOR(20) #define _VECTORS_SIZE 84 / Constants / #define SPM_PAGESIZE 128 #define RAMEND 0x45F #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x3FFF / Fuses / #define FUSE_MEMORY_SIZE 2 / Low Fuse Byte / #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_BODEN (unsigned char)~_BV(6) #define FUSE_BODLEVEL (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) / High Fuse Byte / #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_CKOPT (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) / Lock Bits / #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST / Signature / #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x03 #endif / _AVR_IOM16_H_ */

ATmega32

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[m32def.inc] [iom32.h]

;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** ;***** Created: 2009-11-03 14:40 ******* Source: ATmega32.xml ************ ;************************************************************************* ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y ;* ;* Number : AVR000 ;* File Name : "m32def.inc" ;* Title : Register/Bit Definitions for the ATmega32 ;* Date : 2009-11-03 ;* Version : 2.35 ;* Support E-mail : avr@atmel.com ;* Target MCU : ATmega32 ;* ;* DESCRIPTION ;* When including this file in the assembly program file, all I/O register ;* names and I/O register bit names appearing in the data book can be used. ;* In addition, the six registers forming the three data pointers X, Y and ;* Z have been assigned names XL - ZH. Highest RAM address for Internal ;* SRAM is also defined ;* ;* The Register names are represented by their hexadecimal address. ;* ;* The Register Bit names are represented by their bit number (0-7). ;* ;* Please observe the difference in using the bit names with instructions ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" ;* (skip if bit in register set/cleared). The following example illustrates ;* this: ;* ;* in r16,PORTB ;read PORTB latch ;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) ;* out PORTB,r16 ;output to PORTB ;* ;* in r16,TIFR ;read the Timer Interrupt Flag Register ;* sbrc r16,TOV0 ;test the overflow flag (use bit#) ;* rjmp TOV0_is_set ;jump if set ;* ... ;otherwise do something else ;************************************************************************* #ifndef _M32DEF_INC_ #define _M32DEF_INC_ #pragma partinc 0 ; ***** SPECIFY DEVICE *************************************************** .device ATmega32 #pragma AVRPART ADMIN PART_NAME ATmega32 .equ SIGNATURE_000 = 0x1e .equ SIGNATURE_001 = 0x95 .equ SIGNATURE_002 = 0x02 #pragma AVRPART CORE CORE_VERSION V2E ; ***** I/O REGISTER DEFINITIONS ***************************************** ; NOTE: ; Definitions marked "MEMORY MAPPED"are extended I/O ports ; and cannot be used with IN/OUT instructions .equ SREG = 0x3f .equ SPL = 0x3d .equ SPH = 0x3e .equ OCR0 = 0x3c .equ GICR = 0x3b .equ GIFR = 0x3a .equ TIMSK = 0x39 .equ TIFR = 0x38 .equ SPMCR = 0x37 .equ TWCR = 0x36 .equ MCUCR = 0x35 .equ MCUCSR = 0x34 .equ TCCR0 = 0x33 .equ TCNT0 = 0x32 .equ OSCCAL = 0x31 .equ OCDR = 0x31 .equ SFIOR = 0x30 .equ TCCR1A = 0x2f .equ TCCR1B = 0x2e .equ TCNT1L = 0x2c .equ TCNT1H = 0x2d .equ OCR1AL = 0x2a .equ OCR1AH = 0x2b .equ OCR1BL = 0x28 .equ OCR1BH = 0x29 .equ ICR1L = 0x26 .equ ICR1H = 0x27 .equ TCCR2 = 0x25 .equ TCNT2 = 0x24 .equ OCR2 = 0x23 .equ ASSR = 0x22 .equ WDTCR = 0x21 .equ UBRRH = 0x20 .equ UCSRC = 0x20 .equ EEARL = 0x1e .equ EEARH = 0x1f .equ EEDR = 0x1d .equ EECR = 0x1c .equ PORTA = 0x1b .equ DDRA = 0x1a .equ PINA = 0x19 .equ PORTB = 0x18 .equ DDRB = 0x17 .equ PINB = 0x16 .equ PORTC = 0x15 .equ DDRC = 0x14 .equ PINC = 0x13 .equ PORTD = 0x12 .equ DDRD = 0x11 .equ PIND = 0x10 .equ SPDR = 0x0f .equ SPSR = 0x0e .equ SPCR = 0x0d .equ UDR = 0x0c .equ UCSRA = 0x0b .equ UCSRB = 0x0a .equ UBRRL = 0x09 .equ ACSR = 0x08 .equ ADMUX = 0x07 .equ ADCSRA = 0x06 .equ ADCH = 0x05 .equ ADCL = 0x04 .equ TWDR = 0x03 .equ TWAR = 0x02 .equ TWSR = 0x01 .equ TWBR = 0x00 ; ***** BIT DEFINITIONS ************************************************** ; ***** EEPROM *********************** ; EEDR - EEPROM Data Register .equ EEDR0 = 0 ; EEPROM Data Register bit 0 .equ EEDR1 = 1 ; EEPROM Data Register bit 1 .equ EEDR2 = 2 ; EEPROM Data Register bit 2 .equ EEDR3 = 3 ; EEPROM Data Register bit 3 .equ EEDR4 = 4 ; EEPROM Data Register bit 4 .equ EEDR5 = 5 ; EEPROM Data Register bit 5 .equ EEDR6 = 6 ; EEPROM Data Register bit 6 .equ EEDR7 = 7 ; EEPROM Data Register bit 7 ; EECR - EEPROM Control Register .equ EERE = 0 ; EEPROM Read Enable .equ EEWE = 1 ; EEPROM Write Enable .equ EEMWE = 2 ; EEPROM Master Write Enable .equ EERIE = 3 ; EEPROM Ready Interrupt Enable ; ***** WATCHDOG ********************* ; WDTCR - Watchdog Timer Control Register .equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 .equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 .equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 .equ WDE = 3 ; Watch Dog Enable .equ WDTOE = 4 ; RW .equ WDDE = WDTOE ; For compatibility ; ***** EXTERNAL_INTERRUPT *********** ; GICR - General Interrupt Control Register .equ GIMSK = GICR ; For compatibility .equ IVCE = 0 ; Interrupt Vector Change Enable .equ IVSEL = 1 ; Interrupt Vector Select .equ INT2 = 5 ; External Interrupt Request 2 Enable .equ INT0 = 6 ; External Interrupt Request 0 Enable .equ INT1 = 7 ; External Interrupt Request 1 Enable ; GIFR - General Interrupt Flag Register .equ INTF2 = 5 ; External Interrupt Flag 2 .equ INTF0 = 6 ; External Interrupt Flag 0 .equ INTF1 = 7 ; External Interrupt Flag 1 ; MCUCR - General Interrupt Control Register .equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 .equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 .equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 .equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 ; MCUCSR - MCU Control And Status Register .equ ISC2 = 6 ; Interrupt Sense Control 2 ; ***** TIMER_COUNTER_0 ************** ; TCCR0 - Timer/Counter Control Register .equ CS00 = 0 ; Clock Select 1 .equ CS01 = 1 ; Clock Select 1 .equ CS02 = 2 ; Clock Select 2 .equ WGM01 = 3 ; Waveform Generation Mode 1 .equ CTC0 = WGM01 ; For compatibility .equ COM00 = 4 ; Compare match Output Mode 0 .equ COM01 = 5 ; Compare Match Output Mode 1 .equ WGM00 = 6 ; Waveform Generation Mode .equ PWM0 = WGM00 ; For compatibility .equ FOC0 = 7 ; Force Output Compare ; TCNT0 - Timer/Counter Register .equ TCNT0_0 = 0 ; .equ TCNT0_1 = 1 ; .equ TCNT0_2 = 2 ; .equ TCNT0_3 = 3 ; .equ TCNT0_4 = 4 ; .equ TCNT0_5 = 5 ; .equ TCNT0_6 = 6 ; .equ TCNT0_7 = 7 ; ; OCR0 - Output Compare Register .equ OCR0_0 = 0 ; .equ OCR0_1 = 1 ; .equ OCR0_2 = 2 ; .equ OCR0_3 = 3 ; .equ OCR0_4 = 4 ; .equ OCR0_5 = 5 ; .equ OCR0_6 = 6 ; .equ OCR0_7 = 7 ; ; TIMSK - Timer/Counter Interrupt Mask Register .equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable .equ OCIE0 = 1 ; Timer/Counter0 Output Compare Match Interrupt register ; TIFR - Timer/Counter Interrupt Flag register .equ TOV0 = 0 ; Timer/Counter0 Overflow Flag .equ OCF0 = 1 ; Output Compare Flag 0 ; ***** TIMER_COUNTER_2 ************** ; TIMSK - Timer/Counter Interrupt Mask register .equ TOIE2 = 6 ; Timer/Counter2 Overflow Interrupt Enable .equ OCIE2 = 7 ; Timer/Counter2 Output Compare Match Interrupt Enable ; TIFR - Timer/Counter Interrupt Flag Register .equ TOV2 = 6 ; Timer/Counter2 Overflow Flag .equ OCF2 = 7 ; Output Compare Flag 2 ; TCCR2 - Timer/Counter2 Control Register .equ CS20 = 0 ; Clock Select bit 0 .equ CS21 = 1 ; Clock Select bit 1 .equ CS22 = 2 ; Clock Select bit 2 .equ WGM21 = 3 ; Clear Timer/Counter2 on Compare Match .equ CTC2 = WGM21 ; For compatibility .equ COM20 = 4 ; Compare Output Mode bit 0 .equ COM21 = 5 ; Compare Output Mode bit 1 .equ WGM20 = 6 ; Pulse Width Modulator Enable .equ PWM2 = WGM20 ; For compatibility .equ FOC2 = 7 ; Force Output Compare ; TCNT2 - Timer/Counter2 .equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 .equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 .equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 .equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 .equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 .equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 .equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 .equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 ; OCR2 - Timer/Counter2 Output Compare Register .equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 .equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 .equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 .equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 .equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 .equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 .equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 .equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 ; ASSR - Asynchronous Status Register .equ TCR2UB = 0 ; Timer/counter Control Register2 Update Busy .equ OCR2UB = 1 ; Output Compare Register2 Update Busy .equ TCN2UB = 2 ; Timer/Counter2 Update Busy .equ AS2 = 3 ; Asynchronous Timer/counter2 ; ***** TIMER_COUNTER_1 ************** ; TIMSK - Timer/Counter Interrupt Mask Register .equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable .equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable .equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable .equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable ; TIFR - Timer/Counter Interrupt Flag register .equ TOV1 = 2 ; Timer/Counter1 Overflow Flag .equ OCF1B = 3 ; Output Compare Flag 1B .equ OCF1A = 4 ; Output Compare Flag 1A .equ ICF1 = 5 ; Input Capture Flag 1 ; TCCR1A - Timer/Counter1 Control Register A .equ WGM10 = 0 ; Waveform Generation Mode .equ PWM10 = WGM10 ; For compatibility .equ WGM11 = 1 ; Waveform Generation Mode .equ PWM11 = WGM11 ; For compatibility .equ FOC1B = 2 ; Force Output Compare 1B .equ FOC1A = 3 ; Force Output Compare 1A .equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 .equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 .equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0 .equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 ; TCCR1B - Timer/Counter1 Control Register B .equ CS10 = 0 ; Prescaler source of Timer/Counter 1 .equ CS11 = 1 ; Prescaler source of Timer/Counter 1 .equ CS12 = 2 ; Prescaler source of Timer/Counter 1 .equ WGM12 = 3 ; Waveform Generation Mode .equ CTC10 = WGM12 ; For compatibility .equ CTC1 = WGM12 ; For compatibility .equ WGM13 = 4 ; Waveform Generation Mode .equ CTC11 = WGM13 ; For compatibility .equ ICES1 = 6 ; Input Capture 1 Edge Select .equ ICNC1 = 7 ; Input Capture 1 Noise Canceler ; ***** SPI ************************** ; SPDR - SPI Data Register .equ SPDR0 = 0 ; SPI Data Register bit 0 .equ SPDR1 = 1 ; SPI Data Register bit 1 .equ SPDR2 = 2 ; SPI Data Register bit 2 .equ SPDR3 = 3 ; SPI Data Register bit 3 .equ SPDR4 = 4 ; SPI Data Register bit 4 .equ SPDR5 = 5 ; SPI Data Register bit 5 .equ SPDR6 = 6 ; SPI Data Register bit 6 .equ SPDR7 = 7 ; SPI Data Register bit 7 ; SPSR - SPI Status Register .equ SPI2X = 0 ; Double SPI Speed Bit .equ WCOL = 6 ; Write Collision Flag .equ SPIF = 7 ; SPI Interrupt Flag ; SPCR - SPI Control Register .equ SPR0 = 0 ; SPI Clock Rate Select 0 .equ SPR1 = 1 ; SPI Clock Rate Select 1 .equ CPHA = 2 ; Clock Phase .equ CPOL = 3 ; Clock polarity .equ MSTR = 4 ; Master/Slave Select .equ DORD = 5 ; Data Order .equ SPE = 6 ; SPI Enable .equ SPIE = 7 ; SPI Interrupt Enable ; ***** USART ************************ ; UDR - USART I/O Data Register .equ UDR0 = 0 ; USART I/O Data Register bit 0 .equ UDR1 = 1 ; USART I/O Data Register bit 1 .equ UDR2 = 2 ; USART I/O Data Register bit 2 .equ UDR3 = 3 ; USART I/O Data Register bit 3 .equ UDR4 = 4 ; USART I/O Data Register bit 4 .equ UDR5 = 5 ; USART I/O Data Register bit 5 .equ UDR6 = 6 ; USART I/O Data Register bit 6 .equ UDR7 = 7 ; USART I/O Data Register bit 7 ; UCSRA - USART Control and Status Register A .equ USR = UCSRA ; For compatibility .equ MPCM = 0 ; Multi-processor Communication Mode .equ U2X = 1 ; Double the USART transmission speed .equ UPE = 2 ; Parity Error .equ PE = UPE ; For compatibility .equ DOR = 3 ; Data overRun .equ FE = 4 ; Framing Error .equ UDRE = 5 ; USART Data Register Empty .equ TXC = 6 ; USART Transmitt Complete .equ RXC = 7 ; USART Receive Complete ; UCSRB - USART Control and Status Register B .equ UCR = UCSRB ; For compatibility .equ TXB8 = 0 ; Transmit Data Bit 8 .equ RXB8 = 1 ; Receive Data Bit 8 .equ UCSZ2 = 2 ; Character Size .equ CHR9 = UCSZ2 ; For compatibility .equ TXEN = 3 ; Transmitter Enable .equ RXEN = 4 ; Receiver Enable .equ UDRIE = 5 ; USART Data register Empty Interrupt Enable .equ TXCIE = 6 ; TX Complete Interrupt Enable .equ RXCIE = 7 ; RX Complete Interrupt Enable ; UCSRC - USART Control and Status Register C .equ UCPOL = 0 ; Clock Polarity .equ UCSZ0 = 1 ; Character Size .equ UCSZ1 = 2 ; Character Size .equ USBS = 3 ; Stop Bit Select .equ UPM0 = 4 ; Parity Mode Bit 0 .equ UPM1 = 5 ; Parity Mode Bit 1 .equ UMSEL = 6 ; USART Mode Select .equ URSEL = 7 ; Register Select .equ UBRRHI = UBRRH ; For compatibility ; ***** ANALOG_COMPARATOR ************ ; SFIOR - Special Function IO Register .equ ACME = 3 ; Analog Comparator Multiplexer Enable ; ACSR - Analog Comparator Control And Status Register .equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 .equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 .equ ACIC = 2 ; Analog Comparator Input Capture Enable .equ ACIE = 3 ; Analog Comparator Interrupt Enable .equ ACI = 4 ; Analog Comparator Interrupt Flag .equ ACO = 5 ; Analog Compare Output .equ ACBG = 6 ; Analog Comparator Bandgap Select .equ ACD = 7 ; Analog Comparator Disable ; ***** AD_CONVERTER ***************** ; ADMUX - The ADC multiplexer Selection Register .equ MUX0 = 0 ; Analog Channel and Gain Selection Bits .equ MUX1 = 1 ; Analog Channel and Gain Selection Bits .equ MUX2 = 2 ; Analog Channel and Gain Selection Bits .equ MUX3 = 3 ; Analog Channel and Gain Selection Bits .equ MUX4 = 4 ; Analog Channel and Gain Selection Bits .equ ADLAR = 5 ; Left Adjust Result .equ REFS0 = 6 ; Reference Selection Bit 0 .equ REFS1 = 7 ; Reference Selection Bit 1 ; ADCSRA - The ADC Control and Status register .equ ADCSR = ADCSRA ; For compatibility .equ ADPS0 = 0 ; ADC Prescaler Select Bits .equ ADPS1 = 1 ; ADC Prescaler Select Bits .equ ADPS2 = 2 ; ADC Prescaler Select Bits .equ ADIE = 3 ; ADC Interrupt Enable .equ ADIF = 4 ; ADC Interrupt Flag .equ ADATE = 5 ; When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset. .equ ADFR = ADATE ; For compatibility .equ ADSC = 6 ; ADC Start Conversion .equ ADEN = 7 ; ADC Enable ; ADCH - ADC Data Register High Byte .equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 .equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 .equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 .equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 .equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 .equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 .equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 .equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 ; ADCL - ADC Data Register Low Byte .equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 .equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 .equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 .equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 .equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 .equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 .equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 .equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 ; SFIOR - Special Function IO Register .equ ADTS0 = 5 ; ADC Auto Trigger Source 0 .equ ADTS1 = 6 ; ADC Auto Trigger Source 1 .equ ADTS2 = 7 ; ADC Auto Trigger Source 2 ; ***** PORTA ************************ ; PORTA - Port A Data Register .equ PORTA0 = 0 ; Port A Data Register bit 0 .equ PA0 = 0 ; For compatibility .equ PORTA1 = 1 ; Port A Data Register bit 1 .equ PA1 = 1 ; For compatibility .equ PORTA2 = 2 ; Port A Data Register bit 2 .equ PA2 = 2 ; For compatibility .equ PORTA3 = 3 ; Port A Data Register bit 3 .equ PA3 = 3 ; For compatibility .equ PORTA4 = 4 ; Port A Data Register bit 4 .equ PA4 = 4 ; For compatibility .equ PORTA5 = 5 ; Port A Data Register bit 5 .equ PA5 = 5 ; For compatibility .equ PORTA6 = 6 ; Port A Data Register bit 6 .equ PA6 = 6 ; For compatibility .equ PORTA7 = 7 ; Port A Data Register bit 7 .equ PA7 = 7 ; For compatibility ; DDRA - Port A Data Direction Register .equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 .equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 .equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 .equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 .equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 .equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 .equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 .equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 ; PINA - Port A Input Pins .equ PINA0 = 0 ; Input Pins, Port A bit 0 .equ PINA1 = 1 ; Input Pins, Port A bit 1 .equ PINA2 = 2 ; Input Pins, Port A bit 2 .equ PINA3 = 3 ; Input Pins, Port A bit 3 .equ PINA4 = 4 ; Input Pins, Port A bit 4 .equ PINA5 = 5 ; Input Pins, Port A bit 5 .equ PINA6 = 6 ; Input Pins, Port A bit 6 .equ PINA7 = 7 ; Input Pins, Port A bit 7 ; ***** PORTB ************************ ; PORTB - Port B Data Register .equ PORTB0 = 0 ; Port B Data Register bit 0 .equ PB0 = 0 ; For compatibility .equ PORTB1 = 1 ; Port B Data Register bit 1 .equ PB1 = 1 ; For compatibility .equ PORTB2 = 2 ; Port B Data Register bit 2 .equ PB2 = 2 ; For compatibility .equ PORTB3 = 3 ; Port B Data Register bit 3 .equ PB3 = 3 ; For compatibility .equ PORTB4 = 4 ; Port B Data Register bit 4 .equ PB4 = 4 ; For compatibility .equ PORTB5 = 5 ; Port B Data Register bit 5 .equ PB5 = 5 ; For compatibility .equ PORTB6 = 6 ; Port B Data Register bit 6 .equ PB6 = 6 ; For compatibility .equ PORTB7 = 7 ; Port B Data Register bit 7 .equ PB7 = 7 ; For compatibility ; DDRB - Port B Data Direction Register .equ DDB0 = 0 ; Port B Data Direction Register bit 0 .equ DDB1 = 1 ; Port B Data Direction Register bit 1 .equ DDB2 = 2 ; Port B Data Direction Register bit 2 .equ DDB3 = 3 ; Port B Data Direction Register bit 3 .equ DDB4 = 4 ; Port B Data Direction Register bit 4 .equ DDB5 = 5 ; Port B Data Direction Register bit 5 .equ DDB6 = 6 ; Port B Data Direction Register bit 6 .equ DDB7 = 7 ; Port B Data Direction Register bit 7 ; PINB - Port B Input Pins .equ PINB0 = 0 ; Port B Input Pins bit 0 .equ PINB1 = 1 ; Port B Input Pins bit 1 .equ PINB2 = 2 ; Port B Input Pins bit 2 .equ PINB3 = 3 ; Port B Input Pins bit 3 .equ PINB4 = 4 ; Port B Input Pins bit 4 .equ PINB5 = 5 ; Port B Input Pins bit 5 .equ PINB6 = 6 ; Port B Input Pins bit 6 .equ PINB7 = 7 ; Port B Input Pins bit 7 ; ***** PORTC ************************ ; PORTC - Port C Data Register .equ PORTC0 = 0 ; Port C Data Register bit 0 .equ PC0 = 0 ; For compatibility .equ PORTC1 = 1 ; Port C Data Register bit 1 .equ PC1 = 1 ; For compatibility .equ PORTC2 = 2 ; Port C Data Register bit 2 .equ PC2 = 2 ; For compatibility .equ PORTC3 = 3 ; Port C Data Register bit 3 .equ PC3 = 3 ; For compatibility .equ PORTC4 = 4 ; Port C Data Register bit 4 .equ PC4 = 4 ; For compatibility .equ PORTC5 = 5 ; Port C Data Register bit 5 .equ PC5 = 5 ; For compatibility .equ PORTC6 = 6 ; Port C Data Register bit 6 .equ PC6 = 6 ; For compatibility .equ PORTC7 = 7 ; Port C Data Register bit 7 .equ PC7 = 7 ; For compatibility ; DDRC - Port C Data Direction Register .equ DDC0 = 0 ; Port C Data Direction Register bit 0 .equ DDC1 = 1 ; Port C Data Direction Register bit 1 .equ DDC2 = 2 ; Port C Data Direction Register bit 2 .equ DDC3 = 3 ; Port C Data Direction Register bit 3 .equ DDC4 = 4 ; Port C Data Direction Register bit 4 .equ DDC5 = 5 ; Port C Data Direction Register bit 5 .equ DDC6 = 6 ; Port C Data Direction Register bit 6 .equ DDC7 = 7 ; Port C Data Direction Register bit 7 ; PINC - Port C Input Pins .equ PINC0 = 0 ; Port C Input Pins bit 0 .equ PINC1 = 1 ; Port C Input Pins bit 1 .equ PINC2 = 2 ; Port C Input Pins bit 2 .equ PINC3 = 3 ; Port C Input Pins bit 3 .equ PINC4 = 4 ; Port C Input Pins bit 4 .equ PINC5 = 5 ; Port C Input Pins bit 5 .equ PINC6 = 6 ; Port C Input Pins bit 6 .equ PINC7 = 7 ; Port C Input Pins bit 7 ; ***** PORTD ************************ ; PORTD - Port D Data Register .equ PORTD0 = 0 ; Port D Data Register bit 0 .equ PD0 = 0 ; For compatibility .equ PORTD1 = 1 ; Port D Data Register bit 1 .equ PD1 = 1 ; For compatibility .equ PORTD2 = 2 ; Port D Data Register bit 2 .equ PD2 = 2 ; For compatibility .equ PORTD3 = 3 ; Port D Data Register bit 3 .equ PD3 = 3 ; For compatibility .equ PORTD4 = 4 ; Port D Data Register bit 4 .equ PD4 = 4 ; For compatibility .equ PORTD5 = 5 ; Port D Data Register bit 5 .equ PD5 = 5 ; For compatibility .equ PORTD6 = 6 ; Port D Data Register bit 6 .equ PD6 = 6 ; For compatibility .equ PORTD7 = 7 ; Port D Data Register bit 7 .equ PD7 = 7 ; For compatibility ; DDRD - Port D Data Direction Register .equ DDD0 = 0 ; Port D Data Direction Register bit 0 .equ DDD1 = 1 ; Port D Data Direction Register bit 1 .equ DDD2 = 2 ; Port D Data Direction Register bit 2 .equ DDD3 = 3 ; Port D Data Direction Register bit 3 .equ DDD4 = 4 ; Port D Data Direction Register bit 4 .equ DDD5 = 5 ; Port D Data Direction Register bit 5 .equ DDD6 = 6 ; Port D Data Direction Register bit 6 .equ DDD7 = 7 ; Port D Data Direction Register bit 7 ; PIND - Port D Input Pins .equ PIND0 = 0 ; Port D Input Pins bit 0 .equ PIND1 = 1 ; Port D Input Pins bit 1 .equ PIND2 = 2 ; Port D Input Pins bit 2 .equ PIND3 = 3 ; Port D Input Pins bit 3 .equ PIND4 = 4 ; Port D Input Pins bit 4 .equ PIND5 = 5 ; Port D Input Pins bit 5 .equ PIND6 = 6 ; Port D Input Pins bit 6 .equ PIND7 = 7 ; Port D Input Pins bit 7 ; ***** CPU ************************** ; SREG - Status Register .equ SREG_C = 0 ; Carry Flag .equ SREG_Z = 1 ; Zero Flag .equ SREG_N = 2 ; Negative Flag .equ SREG_V = 3 ; Two's Complement Overflow Flag .equ SREG_S = 4 ; Sign Bit .equ SREG_H = 5 ; Half Carry Flag .equ SREG_T = 6 ; Bit Copy Storage .equ SREG_I = 7 ; Global Interrupt Enable ; MCUCR - MCU Control Register ;.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 ;.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 ;.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 ;.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 .equ SM0 = 4 ; Sleep Mode Select .equ SM1 = 5 ; Sleep Mode Select .equ SM2 = 6 ; Sleep Mode Select .equ SE = 7 ; Sleep Enable ; MCUCSR - MCU Control And Status Register .equ MCUSR = MCUCSR ; For compatibility .equ PORF = 0 ; Power-on reset flag .equ EXTRF = 1 ; External Reset Flag .equ BORF = 2 ; Brown-out Reset Flag .equ WDRF = 3 ; Watchdog Reset Flag .equ JTRF = 4 ; JTAG Reset Flag .equ JTD = 7 ; JTAG Interface Disable ; OSCCAL - Oscillator Calibration Value .equ CAL0 = 0 ; Oscillator Calibration Value Bit0 .equ CAL1 = 1 ; Oscillator Calibration Value Bit1 .equ CAL2 = 2 ; Oscillator Calibration Value Bit2 .equ CAL3 = 3 ; Oscillator Calibration Value Bit3 .equ CAL4 = 4 ; Oscillator Calibration Value Bit4 .equ CAL5 = 5 ; Oscillator Calibration Value Bit5 .equ CAL6 = 6 ; Oscillator Calibration Value Bit6 .equ CAL7 = 7 ; Oscillator Calibration Value Bit7 ; SFIOR - Special Function IO Register .equ PSR10 = 0 ; Prescaler Reset Timer/Counter1&0 .equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 .equ PUD = 2 ; Pull-up Disable ; ***** BOOT_LOAD ******************** ; SPMCR - Store Program Memory Control Register .equ SPMEN = 0 ; Store Program Memory Enable .equ PGERS = 1 ; Page Erase .equ PGWRT = 2 ; Page Write .equ BLBSET = 3 ; Boot Lock Bit Set .equ RWWSRE = 4 ; Read While Write secion read enable .equ ASRE = RWWSRE ; For compatibility .equ RWWSB = 6 ; Read While Write Section Busy .equ ASB = RWWSB ; For compatibility .equ SPMIE = 7 ; SPM Interrupt Enable ; ***** TWI ************************** ; TWBR - TWI Bit Rate register .equ TWBR0 = 0 ; .equ TWBR1 = 1 ; .equ TWBR2 = 2 ; .equ TWBR3 = 3 ; .equ TWBR4 = 4 ; .equ TWBR5 = 5 ; .equ TWBR6 = 6 ; .equ TWBR7 = 7 ; ; TWCR - TWI Control Register .equ TWIE = 0 ; TWI Interrupt Enable .equ TWEN = 2 ; TWI Enable Bit .equ TWWC = 3 ; TWI Write Collition Flag .equ TWSTO = 4 ; TWI Stop Condition Bit .equ TWSTA = 5 ; TWI Start Condition Bit .equ TWEA = 6 ; TWI Enable Acknowledge Bit .equ TWINT = 7 ; TWI Interrupt Flag ; TWSR - TWI Status Register .equ TWPS0 = 0 ; TWI Prescaler bits .equ TWPS1 = 1 ; TWI Prescaler bits .equ TWS3 = 3 ; TWI Status .equ TWS4 = 4 ; TWI Status .equ TWS5 = 5 ; TWI Status .equ TWS6 = 6 ; TWI Status .equ TWS7 = 7 ; TWI Status ; TWDR - TWI Data register .equ TWD0 = 0 ; TWI Data Register Bit 0 .equ TWD1 = 1 ; TWI Data Register Bit 1 .equ TWD2 = 2 ; TWI Data Register Bit 2 .equ TWD3 = 3 ; TWI Data Register Bit 3 .equ TWD4 = 4 ; TWI Data Register Bit 4 .equ TWD5 = 5 ; TWI Data Register Bit 5 .equ TWD6 = 6 ; TWI Data Register Bit 6 .equ TWD7 = 7 ; TWI Data Register Bit 7 ; TWAR - TWI (Slave) Address register .equ TWGCE = 0 ; TWI General Call Recognition Enable Bit .equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 .equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 .equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 .equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 .equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 .equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 .equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 ; ***** LOCKSBITS ******************************************************** .equ LB1 = 0 ; Lock bit .equ LB2 = 1 ; Lock bit .equ BLB01 = 2 ; Boot Lock bit .equ BLB02 = 3 ; Boot Lock bit .equ BLB11 = 4 ; Boot lock bit .equ BLB12 = 5 ; Boot lock bit ; ***** FUSES ************************************************************ ; LOW fuse bits .equ CKSEL0 = 0 ; Select Clock Source .equ CKSEL1 = 1 ; Select Clock Source .equ CKSEL2 = 2 ; Select Clock Source .equ CKSEL3 = 3 ; Select Clock Source .equ BODEN = 6 ; Brown out detector enable .equ BODLEVEL = 7 ; Brown out detector trigger level ; HIGH fuse bits .equ BOOTRST = 0 ; Select Reset Vector .equ BOOTSZ0 = 1 ; Select Boot Size .equ BOOTSZ1 = 2 ; Select Boot Size .equ EESAVE = 3 ; EEPROM memory is preserved through chip erase .equ SPIEN = 5 ; Enable Serial programming and Data Downloading .equ JTAGEN = 6 ; Enable JTAG .equ OCDEN = 7 ; Enable OCD ; ***** CPU REGISTER DEFINITIONS ***************************************** .def XH = r27 .def XL = r26 .def YH = r29 .def YL = r28 .def ZH = r31 .def ZL = r30 ; ***** DATA MEMORY DECLARATIONS ***************************************** .equ FLASHEND = 0x3fff ; Note: Word address .equ IOEND = 0x003f .equ SRAM_START = 0x0060 .equ SRAM_SIZE = 2048 .equ RAMEND = 0x085f .equ XRAMEND = 0x0000 .equ E2END = 0x03ff .equ EEPROMEND = 0x03ff .equ EEADRBITS = 10 #pragma AVRPART MEMORY PROG_FLASH 32768 #pragma AVRPART MEMORY EEPROM 1024 #pragma AVRPART MEMORY INT_SRAM SIZE 2048 #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 ; ***** BOOTLOADER DECLARATIONS ****************************************** .equ NRWW_START_ADDR = 0x3800 .equ NRWW_STOP_ADDR = 0x3fff .equ RWW_START_ADDR = 0x0 .equ RWW_STOP_ADDR = 0x37ff .equ PAGESIZE = 64 .equ FIRSTBOOTSTART = 0x3f00 .equ SECONDBOOTSTART = 0x3e00 .equ THIRDBOOTSTART = 0x3c00 .equ FOURTHBOOTSTART = 0x3800 .equ SMALLBOOTSTART = FIRSTBOOTSTART .equ LARGEBOOTSTART = FOURTHBOOTSTART ; ***** INTERRUPT VECTORS ************************************************ .equ INT0addr = 0x0002 ; External Interrupt Request 0 .equ INT1addr = 0x0004 ; External Interrupt Request 1 .equ INT2addr = 0x0006 ; External Interrupt Request 2 .equ OC2addr = 0x0008 ; Timer/Counter2 Compare Match .equ OVF2addr = 0x000a ; Timer/Counter2 Overflow .equ ICP1addr = 0x000c ; Timer/Counter1 Capture Event .equ OC1Aaddr = 0x000e ; Timer/Counter1 Compare Match A .equ OC1Baddr = 0x0010 ; Timer/Counter1 Compare Match B .equ OVF1addr = 0x0012 ; Timer/Counter1 Overflow .equ OC0addr = 0x0014 ; Timer/Counter0 Compare Match .equ OVF0addr = 0x0016 ; Timer/Counter0 Overflow .equ SPIaddr = 0x0018 ; Serial Transfer Complete .equ URXCaddr = 0x001a ; USART, Rx Complete .equ UDREaddr = 0x001c ; USART Data Register Empty .equ UTXCaddr = 0x001e ; USART, Tx Complete .equ ADCCaddr = 0x0020 ; ADC Conversion Complete .equ ERDYaddr = 0x0022 ; EEPROM Ready .equ ACIaddr = 0x0024 ; Analog Comparator .equ TWIaddr = 0x0026 ; 2-wire Serial Interface .equ SPMRaddr = 0x0028 ; Store Program Memory Ready .equ INT_VECTORS_SIZE = 42 ; size in words #endif /* _M32DEF_INC_ */ ; ***** END OF FILE ****************************************************** /* Copyright (c) 2002, Steinar Haugen All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom32.h,v 1.11.2.6 2009/02/11 18:05:27 arcanum Exp $ */ /* avr/iom32.h - definitions for ATmega32 */ #ifndef _AVR_IOM32_H_ #define _AVR_IOM32_H_ 1 /* This file should only be included from <avr/io.h>, never directly. */ #ifndef _AVR_IO_H_ # error "Include <avr/io.h> instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom32.h" #else # error "Attempt to include more than one <avr/ioXXX.h> file." #endif /* I/O registers */ /* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ #define TWBR _SFR_IO8(0x00) #define TWSR _SFR_IO8(0x01) #define TWAR _SFR_IO8(0x02) #define TWDR _SFR_IO8(0x03) /* ADC */ #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCW _SFR_IO16(0x04) #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) #define ADCSRA _SFR_IO8(0x06) #define ADMUX _SFR_IO8(0x07) /* analog comparator */ #define ACSR _SFR_IO8(0x08) /* USART */ #define UBRRL _SFR_IO8(0x09) #define UCSRB _SFR_IO8(0x0A) #define UCSRA _SFR_IO8(0x0B) #define UDR _SFR_IO8(0x0C) /* SPI */ #define SPCR _SFR_IO8(0x0D) #define SPSR _SFR_IO8(0x0E) #define SPDR _SFR_IO8(0x0F) /* Port D */ #define PIND _SFR_IO8(0x10) #define DDRD _SFR_IO8(0x11) #define PORTD _SFR_IO8(0x12) /* Port C */ #define PINC _SFR_IO8(0x13) #define DDRC _SFR_IO8(0x14) #define PORTC _SFR_IO8(0x15) /* Port B */ #define PINB _SFR_IO8(0x16) #define DDRB _SFR_IO8(0x17) #define PORTB _SFR_IO8(0x18) /* Port A */ #define PINA _SFR_IO8(0x19) #define DDRA _SFR_IO8(0x1A) #define PORTA _SFR_IO8(0x1B) /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEARH _SFR_IO8(0x1F) #define UBRRH _SFR_IO8(0x20) #define UCSRC UBRRH #define WDTCR _SFR_IO8(0x21) #define ASSR _SFR_IO8(0x22) /* Timer 2 */ #define OCR2 _SFR_IO8(0x23) #define TCNT2 _SFR_IO8(0x24) #define TCCR2 _SFR_IO8(0x25) /* Timer 1 */ #define ICR1 _SFR_IO16(0x26) #define ICR1L _SFR_IO8(0x26) #define ICR1H _SFR_IO8(0x27) #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) #define TCCR1B _SFR_IO8(0x2E) #define TCCR1A _SFR_IO8(0x2F) #define SFIOR _SFR_IO8(0x30) #define OSCCAL _SFR_IO8(0x31) #define OCDR OSCCAL /* Timer 0 */ #define TCNT0 _SFR_IO8(0x32) #define TCCR0 _SFR_IO8(0x33) #define MCUSR _SFR_IO8(0x34) #define MCUCSR MCUSR #define MCUCR _SFR_IO8(0x35) #define TWCR _SFR_IO8(0x36) #define SPMCR _SFR_IO8(0x37) #define TIFR _SFR_IO8(0x38) #define TIMSK _SFR_IO8(0x39) #define GIFR _SFR_IO8(0x3A) #define GIMSK _SFR_IO8(0x3B) #define GICR GIMSK #define OCR0 _SFR_IO8(0x3C) /* 0x3D..0x3E SP */ /* 0x3F SREG */ /* Interrupt vectors */ /* External Interrupt Request 0 */ #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt Request 1 */ #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* External Interrupt Request 2 */ #define INT2_vect _VECTOR(3) #define SIG_INTERRUPT2 _VECTOR(3) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE2 _VECTOR(4) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect _VECTOR(5) #define SIG_OVERFLOW2 _VECTOR(5) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect _VECTOR(6) #define SIG_INPUT_CAPTURE1 _VECTOR(6) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1A _VECTOR(7) /* Timer/Counter1 Compare Match B */ #define TIMER1_COMPB_vect _VECTOR(8) #define SIG_OUTPUT_COMPARE1B _VECTOR(8) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect _VECTOR(9) #define SIG_OVERFLOW1 _VECTOR(9) /* Timer/Counter0 Compare Match */ #define TIMER0_COMP_vect _VECTOR(10) #define SIG_OUTPUT_COMPARE0 _VECTOR(10) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect _VECTOR(11) #define SIG_OVERFLOW0 _VECTOR(11) /* Serial Transfer Complete */ #define SPI_STC_vect _VECTOR(12) #define SIG_SPI _VECTOR(12) /* USART, Rx Complete */ #define USART_RXC_vect _VECTOR(13) #define SIG_USART_RECV _VECTOR(13) #define SIG_UART_RECV _VECTOR(13) /* USART Data Register Empty */ #define USART_UDRE_vect _VECTOR(14) #define SIG_USART_DATA _VECTOR(14) #define SIG_UART_DATA _VECTOR(14) /* USART, Tx Complete */ #define USART_TXC_vect _VECTOR(15) #define SIG_USART_TRANS _VECTOR(15) #define SIG_UART_TRANS _VECTOR(15) /* ADC Conversion Complete */ #define ADC_vect _VECTOR(16) #define SIG_ADC _VECTOR(16) /* EEPROM Ready */ #define EE_RDY_vect _VECTOR(17) #define SIG_EEPROM_READY _VECTOR(17) /* Analog Comparator */ #define ANA_COMP_vect _VECTOR(18) #define SIG_COMPARATOR _VECTOR(18) /* 2-wire Serial Interface */ #define TWI_vect _VECTOR(19) #define SIG_2WIRE_SERIAL _VECTOR(19) /* Store Program Memory Ready */ #define SPM_RDY_vect _VECTOR(20) #define SIG_SPM_READY _VECTOR(20) #define _VECTORS_SIZE 84 /* Bit numbers */ /* GICR */ #define INT1 7 #define INT0 6 #define INT2 5 #define IVSEL 1 #define IVCE 0 /* GIFR */ #define INTF1 7 #define INTF0 6 #define INTF2 5 /* TIMSK */ #define OCIE2 7 #define TOIE2 6 #define TICIE1 5 #define OCIE1A 4 #define OCIE1B 3 #define TOIE1 2 #define OCIE0 1 #define TOIE0 0 /* TIFR */ #define OCF2 7 #define TOV2 6 #define ICF1 5 #define OCF1A 4 #define OCF1B 3 #define TOV1 2 #define OCF0 1 #define TOV0 0 /* SPMCR */ #define SPMIE 7 #define RWWSB 6 /* bit 5 reserved */ #define RWWSRE 4 #define BLBSET 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 /* TWCR */ #define TWINT 7 #define TWEA 6 #define TWSTA 5 #define TWSTO 4 #define TWWC 3 #define TWEN 2 /* bit 1 reserved */ #define TWIE 0 /* TWAR */ #define TWA6 7 #define TWA5 6 #define TWA4 5 #define TWA3 4 #define TWA2 3 #define TWA1 2 #define TWA0 1 #define TWGCE 0 /* TWSR */ #define TWS7 7 #define TWS6 6 #define TWS5 5 #define TWS4 4 #define TWS3 3 /* bit 2 reserved */ #define TWPS1 1 #define TWPS0 0 /* MCUCR */ #define SE 7 #define SM2 6 #define SM1 5 #define SM0 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* MCUCSR */ #define JTD 7 #define ISC2 6 /* bit 5 reserved */ #define JTRF 4 #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 /* SFIOR */ #define ADTS2 7 #define ADTS1 6 #define ADTS0 5 /* bit 4 reserved */ #define ACME 3 #define PUD 2 #define PSR2 1 #define PSR10 0 /* TCCR0 */ #define FOC0 7 #define WGM00 6 #define COM01 5 #define COM00 4 #define WGM01 3 #define CS02 2 #define CS01 1 #define CS00 0 /* TCCR2 */ #define FOC2 7 #define WGM20 6 #define COM21 5 #define COM20 4 #define WGM21 3 #define CS22 2 #define CS21 1 #define CS20 0 /* ASSR */ /* bits 7-4 reserved */ #define AS2 3 #define TCN2UB 2 #define OCR2UB 1 #define TCR2UB 0 /* TCCR1A */ #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define FOC1A 3 #define FOC1B 2 #define WGM11 1 #define WGM10 0 /* TCCR1B */ #define ICNC1 7 #define ICES1 6 /* bit 5 reserved */ #define WGM13 4 #define WGM12 3 #define CS12 2 #define CS11 1 #define CS10 0 /* WDTCR */ /* bits 7-5 reserved */ #define WDTOE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* PA7-PA0 = ADC7-ADC0 */ /* PORTA */ #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 /* DDRA */ #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 /* PINA */ #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 /* PB7 = SCK PB6 = MISO PB5 = MOSI PB4 = SS# PB3 = OC0/AIN1 PB2 = INT2/AIN0 PB1 = T1 PB0 = XCK/T0 */ /* PORTB */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* DDRB */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* PINB */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* PC7 = TOSC2 PC6 = TOSC1 PC1 = SDA PC0 = SCL */ /* PORTC */ #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* DDRC */ #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 /* PINC */ #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 /* PD7 = OC2 PD6 = ICP PD5 = OC1A PD4 = OC1B PD3 = INT1 PD2 = INT0 PD1 = TXD PD0 = RXD */ /* PORTD */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* DDRD */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* PIND */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* SPSR */ #define SPIF 7 #define WCOL 6 /* bits 5-1 reserved */ #define SPI2X 0 /* SPCR */ #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 /* UCSRA */ #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 #define PE 2 #define U2X 1 #define MPCM 0 /* UCSRB */ #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define UCSZ2 2 #define RXB8 1 #define TXB8 0 /* UCSRC */ #define URSEL 7 #define UMSEL 6 #define UPM1 5 #define UPM0 4 #define USBS 3 #define UCSZ1 2 #define UCSZ0 1 #define UCPOL 0 /* ACSR */ #define ACD 7 #define ACBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 /* ADCSRA */ #define ADEN 7 #define ADSC 6 #define ADATE 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 /* ADMUX */ #define REFS1 7 #define REFS0 6 #define ADLAR 5 #define MUX4 4 #define MUX3 3 #define MUX2 2 #define MUX1 1 #define MUX0 0 /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* Constants */ #define SPM_PAGESIZE 128 #define RAMEND 0x85F #define XRAMEND RAMEND #define E2END 0x3FF #define E2PAGESIZE 4 #define FLASHEND 0x7FFF /* Fuses */ #define FUSE_MEMORY_SIZE 2 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_BODEN (unsigned char)~_BV(6) #define FUSE_BODLEVEL (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_CKOPT (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x95 #define SIGNATURE_2 0x02 #endif /* _AVR_IOM32_H_ */

[m32def.inc]	[iom32.h]
;*** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT **************** ;* Created: 2009-11-03 14:40 *** Source: ATmega32.xml ******** ;*********************************************************************** ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y ;* ;* Number : AVR000 ;* File Name : "m32def.inc" ;* Title : Register/Bit Definitions for the ATmega32 ;* Date : 2009-11-03 ;* Version : 2.35 ;* Support E-mail : avr@atmel.com ;* Target MCU : ATmega32 ;* ;* DESCRIPTION ;* When including this file in the assembly program file, all I/O register ;* names and I/O register bit names appearing in the data book can be used. ;* In addition, the six registers forming the three data pointers X, Y and ;* Z have been assigned names XL - ZH. Highest RAM address for Internal ;* SRAM is also defined ;* ;* The Register names are represented by their hexadecimal address. ;* ;* The Register Bit names are represented by their bit number (0-7). ;* ;* Please observe the difference in using the bit names with instructions ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" ;* (skip if bit in register set/cleared). The following example illustrates ;* this: ;* ;* in r16,PORTB ;read PORTB latch ;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) ;* out PORTB,r16 ;output to PORTB ;* ;* in r16,TIFR ;read the Timer Interrupt Flag Register ;* sbrc r16,TOV0 ;test the overflow flag (use bit#) ;* rjmp TOV0_is_set ;jump if set ;* ... ;otherwise do something else ;*********************************************************************** #ifndef _M32DEF_INC_ #define _M32DEF_INC_ #pragma partinc 0 ; * SPECIFY DEVICE *********************************************** .device ATmega32 #pragma AVRPART ADMIN PART_NAME ATmega32 .equ SIGNATURE_000 = 0x1e .equ SIGNATURE_001 = 0x95 .equ SIGNATURE_002 = 0x02 #pragma AVRPART CORE CORE_VERSION V2E ; * I/O REGISTER DEFINITIONS ************************************* ; NOTE: ; Definitions marked "MEMORY MAPPED"are extended I/O ports ; and cannot be used with IN/OUT instructions .equ SREG = 0x3f .equ SPL = 0x3d .equ SPH = 0x3e .equ OCR0 = 0x3c .equ GICR = 0x3b .equ GIFR = 0x3a .equ TIMSK = 0x39 .equ TIFR = 0x38 .equ SPMCR = 0x37 .equ TWCR = 0x36 .equ MCUCR = 0x35 .equ MCUCSR = 0x34 .equ TCCR0 = 0x33 .equ TCNT0 = 0x32 .equ OSCCAL = 0x31 .equ OCDR = 0x31 .equ SFIOR = 0x30 .equ TCCR1A = 0x2f .equ TCCR1B = 0x2e .equ TCNT1L = 0x2c .equ TCNT1H = 0x2d .equ OCR1AL = 0x2a .equ OCR1AH = 0x2b .equ OCR1BL = 0x28 .equ OCR1BH = 0x29 .equ ICR1L = 0x26 .equ ICR1H = 0x27 .equ TCCR2 = 0x25 .equ TCNT2 = 0x24 .equ OCR2 = 0x23 .equ ASSR = 0x22 .equ WDTCR = 0x21 .equ UBRRH = 0x20 .equ UCSRC = 0x20 .equ EEARL = 0x1e .equ EEARH = 0x1f .equ EEDR = 0x1d .equ EECR = 0x1c .equ PORTA = 0x1b .equ DDRA = 0x1a .equ PINA = 0x19 .equ PORTB = 0x18 .equ DDRB = 0x17 .equ PINB = 0x16 .equ PORTC = 0x15 .equ DDRC = 0x14 .equ PINC = 0x13 .equ PORTD = 0x12 .equ DDRD = 0x11 .equ PIND = 0x10 .equ SPDR = 0x0f .equ SPSR = 0x0e .equ SPCR = 0x0d .equ UDR = 0x0c .equ UCSRA = 0x0b .equ UCSRB = 0x0a .equ UBRRL = 0x09 .equ ACSR = 0x08 .equ ADMUX = 0x07 .equ ADCSRA = 0x06 .equ ADCH = 0x05 .equ ADCL = 0x04 .equ TWDR = 0x03 .equ TWAR = 0x02 .equ TWSR = 0x01 .equ TWBR = 0x00 ; * BIT DEFINITIONS ********************************************** ; * EEPROM ******************* ; EEDR - EEPROM Data Register .equ EEDR0 = 0 ; EEPROM Data Register bit 0 .equ EEDR1 = 1 ; EEPROM Data Register bit 1 .equ EEDR2 = 2 ; EEPROM Data Register bit 2 .equ EEDR3 = 3 ; EEPROM Data Register bit 3 .equ EEDR4 = 4 ; EEPROM Data Register bit 4 .equ EEDR5 = 5 ; EEPROM Data Register bit 5 .equ EEDR6 = 6 ; EEPROM Data Register bit 6 .equ EEDR7 = 7 ; EEPROM Data Register bit 7 ; EECR - EEPROM Control Register .equ EERE = 0 ; EEPROM Read Enable .equ EEWE = 1 ; EEPROM Write Enable .equ EEMWE = 2 ; EEPROM Master Write Enable .equ EERIE = 3 ; EEPROM Ready Interrupt Enable ; * WATCHDOG ***************** ; WDTCR - Watchdog Timer Control Register .equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 .equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 .equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 .equ WDE = 3 ; Watch Dog Enable .equ WDTOE = 4 ; RW .equ WDDE = WDTOE ; For compatibility ; * EXTERNAL_INTERRUPT ******* ; GICR - General Interrupt Control Register .equ GIMSK = GICR ; For compatibility .equ IVCE = 0 ; Interrupt Vector Change Enable .equ IVSEL = 1 ; Interrupt Vector Select .equ INT2 = 5 ; External Interrupt Request 2 Enable .equ INT0 = 6 ; External Interrupt Request 0 Enable .equ INT1 = 7 ; External Interrupt Request 1 Enable ; GIFR - General Interrupt Flag Register .equ INTF2 = 5 ; External Interrupt Flag 2 .equ INTF0 = 6 ; External Interrupt Flag 0 .equ INTF1 = 7 ; External Interrupt Flag 1 ; MCUCR - General Interrupt Control Register .equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 .equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 .equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 .equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 ; MCUCSR - MCU Control And Status Register .equ ISC2 = 6 ; Interrupt Sense Control 2 ; * TIMER_COUNTER_0 ********** ; TCCR0 - Timer/Counter Control Register .equ CS00 = 0 ; Clock Select 1 .equ CS01 = 1 ; Clock Select 1 .equ CS02 = 2 ; Clock Select 2 .equ WGM01 = 3 ; Waveform Generation Mode 1 .equ CTC0 = WGM01 ; For compatibility .equ COM00 = 4 ; Compare match Output Mode 0 .equ COM01 = 5 ; Compare Match Output Mode 1 .equ WGM00 = 6 ; Waveform Generation Mode .equ PWM0 = WGM00 ; For compatibility .equ FOC0 = 7 ; Force Output Compare ; TCNT0 - Timer/Counter Register .equ TCNT0_0 = 0 ; .equ TCNT0_1 = 1 ; .equ TCNT0_2 = 2 ; .equ TCNT0_3 = 3 ; .equ TCNT0_4 = 4 ; .equ TCNT0_5 = 5 ; .equ TCNT0_6 = 6 ; .equ TCNT0_7 = 7 ; ; OCR0 - Output Compare Register .equ OCR0_0 = 0 ; .equ OCR0_1 = 1 ; .equ OCR0_2 = 2 ; .equ OCR0_3 = 3 ; .equ OCR0_4 = 4 ; .equ OCR0_5 = 5 ; .equ OCR0_6 = 6 ; .equ OCR0_7 = 7 ; ; TIMSK - Timer/Counter Interrupt Mask Register .equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable .equ OCIE0 = 1 ; Timer/Counter0 Output Compare Match Interrupt register ; TIFR - Timer/Counter Interrupt Flag register .equ TOV0 = 0 ; Timer/Counter0 Overflow Flag .equ OCF0 = 1 ; Output Compare Flag 0 ; * TIMER_COUNTER_2 ********** ; TIMSK - Timer/Counter Interrupt Mask register .equ TOIE2 = 6 ; Timer/Counter2 Overflow Interrupt Enable .equ OCIE2 = 7 ; Timer/Counter2 Output Compare Match Interrupt Enable ; TIFR - Timer/Counter Interrupt Flag Register .equ TOV2 = 6 ; Timer/Counter2 Overflow Flag .equ OCF2 = 7 ; Output Compare Flag 2 ; TCCR2 - Timer/Counter2 Control Register .equ CS20 = 0 ; Clock Select bit 0 .equ CS21 = 1 ; Clock Select bit 1 .equ CS22 = 2 ; Clock Select bit 2 .equ WGM21 = 3 ; Clear Timer/Counter2 on Compare Match .equ CTC2 = WGM21 ; For compatibility .equ COM20 = 4 ; Compare Output Mode bit 0 .equ COM21 = 5 ; Compare Output Mode bit 1 .equ WGM20 = 6 ; Pulse Width Modulator Enable .equ PWM2 = WGM20 ; For compatibility .equ FOC2 = 7 ; Force Output Compare ; TCNT2 - Timer/Counter2 .equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 .equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 .equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 .equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 .equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 .equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 .equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 .equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 ; OCR2 - Timer/Counter2 Output Compare Register .equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 .equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 .equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 .equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 .equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 .equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 .equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 .equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 ; ASSR - Asynchronous Status Register .equ TCR2UB = 0 ; Timer/counter Control Register2 Update Busy .equ OCR2UB = 1 ; Output Compare Register2 Update Busy .equ TCN2UB = 2 ; Timer/Counter2 Update Busy .equ AS2 = 3 ; Asynchronous Timer/counter2 ; * TIMER_COUNTER_1 ********** ; TIMSK - Timer/Counter Interrupt Mask Register .equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable .equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable .equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable .equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable ; TIFR - Timer/Counter Interrupt Flag register .equ TOV1 = 2 ; Timer/Counter1 Overflow Flag .equ OCF1B = 3 ; Output Compare Flag 1B .equ OCF1A = 4 ; Output Compare Flag 1A .equ ICF1 = 5 ; Input Capture Flag 1 ; TCCR1A - Timer/Counter1 Control Register A .equ WGM10 = 0 ; Waveform Generation Mode .equ PWM10 = WGM10 ; For compatibility .equ WGM11 = 1 ; Waveform Generation Mode .equ PWM11 = WGM11 ; For compatibility .equ FOC1B = 2 ; Force Output Compare 1B .equ FOC1A = 3 ; Force Output Compare 1A .equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 .equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 .equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0 .equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 ; TCCR1B - Timer/Counter1 Control Register B .equ CS10 = 0 ; Prescaler source of Timer/Counter 1 .equ CS11 = 1 ; Prescaler source of Timer/Counter 1 .equ CS12 = 2 ; Prescaler source of Timer/Counter 1 .equ WGM12 = 3 ; Waveform Generation Mode .equ CTC10 = WGM12 ; For compatibility .equ CTC1 = WGM12 ; For compatibility .equ WGM13 = 4 ; Waveform Generation Mode .equ CTC11 = WGM13 ; For compatibility .equ ICES1 = 6 ; Input Capture 1 Edge Select .equ ICNC1 = 7 ; Input Capture 1 Noise Canceler ; * SPI ********************** ; SPDR - SPI Data Register .equ SPDR0 = 0 ; SPI Data Register bit 0 .equ SPDR1 = 1 ; SPI Data Register bit 1 .equ SPDR2 = 2 ; SPI Data Register bit 2 .equ SPDR3 = 3 ; SPI Data Register bit 3 .equ SPDR4 = 4 ; SPI Data Register bit 4 .equ SPDR5 = 5 ; SPI Data Register bit 5 .equ SPDR6 = 6 ; SPI Data Register bit 6 .equ SPDR7 = 7 ; SPI Data Register bit 7 ; SPSR - SPI Status Register .equ SPI2X = 0 ; Double SPI Speed Bit .equ WCOL = 6 ; Write Collision Flag .equ SPIF = 7 ; SPI Interrupt Flag ; SPCR - SPI Control Register .equ SPR0 = 0 ; SPI Clock Rate Select 0 .equ SPR1 = 1 ; SPI Clock Rate Select 1 .equ CPHA = 2 ; Clock Phase .equ CPOL = 3 ; Clock polarity .equ MSTR = 4 ; Master/Slave Select .equ DORD = 5 ; Data Order .equ SPE = 6 ; SPI Enable .equ SPIE = 7 ; SPI Interrupt Enable ; * USART ******************** ; UDR - USART I/O Data Register .equ UDR0 = 0 ; USART I/O Data Register bit 0 .equ UDR1 = 1 ; USART I/O Data Register bit 1 .equ UDR2 = 2 ; USART I/O Data Register bit 2 .equ UDR3 = 3 ; USART I/O Data Register bit 3 .equ UDR4 = 4 ; USART I/O Data Register bit 4 .equ UDR5 = 5 ; USART I/O Data Register bit 5 .equ UDR6 = 6 ; USART I/O Data Register bit 6 .equ UDR7 = 7 ; USART I/O Data Register bit 7 ; UCSRA - USART Control and Status Register A .equ USR = UCSRA ; For compatibility .equ MPCM = 0 ; Multi-processor Communication Mode .equ U2X = 1 ; Double the USART transmission speed .equ UPE = 2 ; Parity Error .equ PE = UPE ; For compatibility .equ DOR = 3 ; Data overRun .equ FE = 4 ; Framing Error .equ UDRE = 5 ; USART Data Register Empty .equ TXC = 6 ; USART Transmitt Complete .equ RXC = 7 ; USART Receive Complete ; UCSRB - USART Control and Status Register B .equ UCR = UCSRB ; For compatibility .equ TXB8 = 0 ; Transmit Data Bit 8 .equ RXB8 = 1 ; Receive Data Bit 8 .equ UCSZ2 = 2 ; Character Size .equ CHR9 = UCSZ2 ; For compatibility .equ TXEN = 3 ; Transmitter Enable .equ RXEN = 4 ; Receiver Enable .equ UDRIE = 5 ; USART Data register Empty Interrupt Enable .equ TXCIE = 6 ; TX Complete Interrupt Enable .equ RXCIE = 7 ; RX Complete Interrupt Enable ; UCSRC - USART Control and Status Register C .equ UCPOL = 0 ; Clock Polarity .equ UCSZ0 = 1 ; Character Size .equ UCSZ1 = 2 ; Character Size .equ USBS = 3 ; Stop Bit Select .equ UPM0 = 4 ; Parity Mode Bit 0 .equ UPM1 = 5 ; Parity Mode Bit 1 .equ UMSEL = 6 ; USART Mode Select .equ URSEL = 7 ; Register Select .equ UBRRHI = UBRRH ; For compatibility ; * ANALOG_COMPARATOR ******** ; SFIOR - Special Function IO Register .equ ACME = 3 ; Analog Comparator Multiplexer Enable ; ACSR - Analog Comparator Control And Status Register .equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 .equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 .equ ACIC = 2 ; Analog Comparator Input Capture Enable .equ ACIE = 3 ; Analog Comparator Interrupt Enable .equ ACI = 4 ; Analog Comparator Interrupt Flag .equ ACO = 5 ; Analog Compare Output .equ ACBG = 6 ; Analog Comparator Bandgap Select .equ ACD = 7 ; Analog Comparator Disable ; * AD_CONVERTER ************* ; ADMUX - The ADC multiplexer Selection Register .equ MUX0 = 0 ; Analog Channel and Gain Selection Bits .equ MUX1 = 1 ; Analog Channel and Gain Selection Bits .equ MUX2 = 2 ; Analog Channel and Gain Selection Bits .equ MUX3 = 3 ; Analog Channel and Gain Selection Bits .equ MUX4 = 4 ; Analog Channel and Gain Selection Bits .equ ADLAR = 5 ; Left Adjust Result .equ REFS0 = 6 ; Reference Selection Bit 0 .equ REFS1 = 7 ; Reference Selection Bit 1 ; ADCSRA - The ADC Control and Status register .equ ADCSR = ADCSRA ; For compatibility .equ ADPS0 = 0 ; ADC Prescaler Select Bits .equ ADPS1 = 1 ; ADC Prescaler Select Bits .equ ADPS2 = 2 ; ADC Prescaler Select Bits .equ ADIE = 3 ; ADC Interrupt Enable .equ ADIF = 4 ; ADC Interrupt Flag .equ ADATE = 5 ; When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset. .equ ADFR = ADATE ; For compatibility .equ ADSC = 6 ; ADC Start Conversion .equ ADEN = 7 ; ADC Enable ; ADCH - ADC Data Register High Byte .equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 .equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 .equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 .equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 .equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 .equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 .equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 .equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 ; ADCL - ADC Data Register Low Byte .equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 .equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 .equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 .equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 .equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 .equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 .equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 .equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 ; SFIOR - Special Function IO Register .equ ADTS0 = 5 ; ADC Auto Trigger Source 0 .equ ADTS1 = 6 ; ADC Auto Trigger Source 1 .equ ADTS2 = 7 ; ADC Auto Trigger Source 2 ; * PORTA ******************** ; PORTA - Port A Data Register .equ PORTA0 = 0 ; Port A Data Register bit 0 .equ PA0 = 0 ; For compatibility .equ PORTA1 = 1 ; Port A Data Register bit 1 .equ PA1 = 1 ; For compatibility .equ PORTA2 = 2 ; Port A Data Register bit 2 .equ PA2 = 2 ; For compatibility .equ PORTA3 = 3 ; Port A Data Register bit 3 .equ PA3 = 3 ; For compatibility .equ PORTA4 = 4 ; Port A Data Register bit 4 .equ PA4 = 4 ; For compatibility .equ PORTA5 = 5 ; Port A Data Register bit 5 .equ PA5 = 5 ; For compatibility .equ PORTA6 = 6 ; Port A Data Register bit 6 .equ PA6 = 6 ; For compatibility .equ PORTA7 = 7 ; Port A Data Register bit 7 .equ PA7 = 7 ; For compatibility ; DDRA - Port A Data Direction Register .equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 .equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 .equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 .equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 .equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 .equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 .equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 .equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 ; PINA - Port A Input Pins .equ PINA0 = 0 ; Input Pins, Port A bit 0 .equ PINA1 = 1 ; Input Pins, Port A bit 1 .equ PINA2 = 2 ; Input Pins, Port A bit 2 .equ PINA3 = 3 ; Input Pins, Port A bit 3 .equ PINA4 = 4 ; Input Pins, Port A bit 4 .equ PINA5 = 5 ; Input Pins, Port A bit 5 .equ PINA6 = 6 ; Input Pins, Port A bit 6 .equ PINA7 = 7 ; Input Pins, Port A bit 7 ; * PORTB ******************** ; PORTB - Port B Data Register .equ PORTB0 = 0 ; Port B Data Register bit 0 .equ PB0 = 0 ; For compatibility .equ PORTB1 = 1 ; Port B Data Register bit 1 .equ PB1 = 1 ; For compatibility .equ PORTB2 = 2 ; Port B Data Register bit 2 .equ PB2 = 2 ; For compatibility .equ PORTB3 = 3 ; Port B Data Register bit 3 .equ PB3 = 3 ; For compatibility .equ PORTB4 = 4 ; Port B Data Register bit 4 .equ PB4 = 4 ; For compatibility .equ PORTB5 = 5 ; Port B Data Register bit 5 .equ PB5 = 5 ; For compatibility .equ PORTB6 = 6 ; Port B Data Register bit 6 .equ PB6 = 6 ; For compatibility .equ PORTB7 = 7 ; Port B Data Register bit 7 .equ PB7 = 7 ; For compatibility ; DDRB - Port B Data Direction Register .equ DDB0 = 0 ; Port B Data Direction Register bit 0 .equ DDB1 = 1 ; Port B Data Direction Register bit 1 .equ DDB2 = 2 ; Port B Data Direction Register bit 2 .equ DDB3 = 3 ; Port B Data Direction Register bit 3 .equ DDB4 = 4 ; Port B Data Direction Register bit 4 .equ DDB5 = 5 ; Port B Data Direction Register bit 5 .equ DDB6 = 6 ; Port B Data Direction Register bit 6 .equ DDB7 = 7 ; Port B Data Direction Register bit 7 ; PINB - Port B Input Pins .equ PINB0 = 0 ; Port B Input Pins bit 0 .equ PINB1 = 1 ; Port B Input Pins bit 1 .equ PINB2 = 2 ; Port B Input Pins bit 2 .equ PINB3 = 3 ; Port B Input Pins bit 3 .equ PINB4 = 4 ; Port B Input Pins bit 4 .equ PINB5 = 5 ; Port B Input Pins bit 5 .equ PINB6 = 6 ; Port B Input Pins bit 6 .equ PINB7 = 7 ; Port B Input Pins bit 7 ; * PORTC ******************** ; PORTC - Port C Data Register .equ PORTC0 = 0 ; Port C Data Register bit 0 .equ PC0 = 0 ; For compatibility .equ PORTC1 = 1 ; Port C Data Register bit 1 .equ PC1 = 1 ; For compatibility .equ PORTC2 = 2 ; Port C Data Register bit 2 .equ PC2 = 2 ; For compatibility .equ PORTC3 = 3 ; Port C Data Register bit 3 .equ PC3 = 3 ; For compatibility .equ PORTC4 = 4 ; Port C Data Register bit 4 .equ PC4 = 4 ; For compatibility .equ PORTC5 = 5 ; Port C Data Register bit 5 .equ PC5 = 5 ; For compatibility .equ PORTC6 = 6 ; Port C Data Register bit 6 .equ PC6 = 6 ; For compatibility .equ PORTC7 = 7 ; Port C Data Register bit 7 .equ PC7 = 7 ; For compatibility ; DDRC - Port C Data Direction Register .equ DDC0 = 0 ; Port C Data Direction Register bit 0 .equ DDC1 = 1 ; Port C Data Direction Register bit 1 .equ DDC2 = 2 ; Port C Data Direction Register bit 2 .equ DDC3 = 3 ; Port C Data Direction Register bit 3 .equ DDC4 = 4 ; Port C Data Direction Register bit 4 .equ DDC5 = 5 ; Port C Data Direction Register bit 5 .equ DDC6 = 6 ; Port C Data Direction Register bit 6 .equ DDC7 = 7 ; Port C Data Direction Register bit 7 ; PINC - Port C Input Pins .equ PINC0 = 0 ; Port C Input Pins bit 0 .equ PINC1 = 1 ; Port C Input Pins bit 1 .equ PINC2 = 2 ; Port C Input Pins bit 2 .equ PINC3 = 3 ; Port C Input Pins bit 3 .equ PINC4 = 4 ; Port C Input Pins bit 4 .equ PINC5 = 5 ; Port C Input Pins bit 5 .equ PINC6 = 6 ; Port C Input Pins bit 6 .equ PINC7 = 7 ; Port C Input Pins bit 7 ; * PORTD ******************** ; PORTD - Port D Data Register .equ PORTD0 = 0 ; Port D Data Register bit 0 .equ PD0 = 0 ; For compatibility .equ PORTD1 = 1 ; Port D Data Register bit 1 .equ PD1 = 1 ; For compatibility .equ PORTD2 = 2 ; Port D Data Register bit 2 .equ PD2 = 2 ; For compatibility .equ PORTD3 = 3 ; Port D Data Register bit 3 .equ PD3 = 3 ; For compatibility .equ PORTD4 = 4 ; Port D Data Register bit 4 .equ PD4 = 4 ; For compatibility .equ PORTD5 = 5 ; Port D Data Register bit 5 .equ PD5 = 5 ; For compatibility .equ PORTD6 = 6 ; Port D Data Register bit 6 .equ PD6 = 6 ; For compatibility .equ PORTD7 = 7 ; Port D Data Register bit 7 .equ PD7 = 7 ; For compatibility ; DDRD - Port D Data Direction Register .equ DDD0 = 0 ; Port D Data Direction Register bit 0 .equ DDD1 = 1 ; Port D Data Direction Register bit 1 .equ DDD2 = 2 ; Port D Data Direction Register bit 2 .equ DDD3 = 3 ; Port D Data Direction Register bit 3 .equ DDD4 = 4 ; Port D Data Direction Register bit 4 .equ DDD5 = 5 ; Port D Data Direction Register bit 5 .equ DDD6 = 6 ; Port D Data Direction Register bit 6 .equ DDD7 = 7 ; Port D Data Direction Register bit 7 ; PIND - Port D Input Pins .equ PIND0 = 0 ; Port D Input Pins bit 0 .equ PIND1 = 1 ; Port D Input Pins bit 1 .equ PIND2 = 2 ; Port D Input Pins bit 2 .equ PIND3 = 3 ; Port D Input Pins bit 3 .equ PIND4 = 4 ; Port D Input Pins bit 4 .equ PIND5 = 5 ; Port D Input Pins bit 5 .equ PIND6 = 6 ; Port D Input Pins bit 6 .equ PIND7 = 7 ; Port D Input Pins bit 7 ; * CPU ********************** ; SREG - Status Register .equ SREG_C = 0 ; Carry Flag .equ SREG_Z = 1 ; Zero Flag .equ SREG_N = 2 ; Negative Flag .equ SREG_V = 3 ; Two's Complement Overflow Flag .equ SREG_S = 4 ; Sign Bit .equ SREG_H = 5 ; Half Carry Flag .equ SREG_T = 6 ; Bit Copy Storage .equ SREG_I = 7 ; Global Interrupt Enable ; MCUCR - MCU Control Register ;.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 ;.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 ;.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 ;.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 .equ SM0 = 4 ; Sleep Mode Select .equ SM1 = 5 ; Sleep Mode Select .equ SM2 = 6 ; Sleep Mode Select .equ SE = 7 ; Sleep Enable ; MCUCSR - MCU Control And Status Register .equ MCUSR = MCUCSR ; For compatibility .equ PORF = 0 ; Power-on reset flag .equ EXTRF = 1 ; External Reset Flag .equ BORF = 2 ; Brown-out Reset Flag .equ WDRF = 3 ; Watchdog Reset Flag .equ JTRF = 4 ; JTAG Reset Flag .equ JTD = 7 ; JTAG Interface Disable ; OSCCAL - Oscillator Calibration Value .equ CAL0 = 0 ; Oscillator Calibration Value Bit0 .equ CAL1 = 1 ; Oscillator Calibration Value Bit1 .equ CAL2 = 2 ; Oscillator Calibration Value Bit2 .equ CAL3 = 3 ; Oscillator Calibration Value Bit3 .equ CAL4 = 4 ; Oscillator Calibration Value Bit4 .equ CAL5 = 5 ; Oscillator Calibration Value Bit5 .equ CAL6 = 6 ; Oscillator Calibration Value Bit6 .equ CAL7 = 7 ; Oscillator Calibration Value Bit7 ; SFIOR - Special Function IO Register .equ PSR10 = 0 ; Prescaler Reset Timer/Counter1&0 .equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 .equ PUD = 2 ; Pull-up Disable ; * BOOT_LOAD **************** ; SPMCR - Store Program Memory Control Register .equ SPMEN = 0 ; Store Program Memory Enable .equ PGERS = 1 ; Page Erase .equ PGWRT = 2 ; Page Write .equ BLBSET = 3 ; Boot Lock Bit Set .equ RWWSRE = 4 ; Read While Write secion read enable .equ ASRE = RWWSRE ; For compatibility .equ RWWSB = 6 ; Read While Write Section Busy .equ ASB = RWWSB ; For compatibility .equ SPMIE = 7 ; SPM Interrupt Enable ; * TWI ********************** ; TWBR - TWI Bit Rate register .equ TWBR0 = 0 ; .equ TWBR1 = 1 ; .equ TWBR2 = 2 ; .equ TWBR3 = 3 ; .equ TWBR4 = 4 ; .equ TWBR5 = 5 ; .equ TWBR6 = 6 ; .equ TWBR7 = 7 ; ; TWCR - TWI Control Register .equ TWIE = 0 ; TWI Interrupt Enable .equ TWEN = 2 ; TWI Enable Bit .equ TWWC = 3 ; TWI Write Collition Flag .equ TWSTO = 4 ; TWI Stop Condition Bit .equ TWSTA = 5 ; TWI Start Condition Bit .equ TWEA = 6 ; TWI Enable Acknowledge Bit .equ TWINT = 7 ; TWI Interrupt Flag ; TWSR - TWI Status Register .equ TWPS0 = 0 ; TWI Prescaler bits .equ TWPS1 = 1 ; TWI Prescaler bits .equ TWS3 = 3 ; TWI Status .equ TWS4 = 4 ; TWI Status .equ TWS5 = 5 ; TWI Status .equ TWS6 = 6 ; TWI Status .equ TWS7 = 7 ; TWI Status ; TWDR - TWI Data register .equ TWD0 = 0 ; TWI Data Register Bit 0 .equ TWD1 = 1 ; TWI Data Register Bit 1 .equ TWD2 = 2 ; TWI Data Register Bit 2 .equ TWD3 = 3 ; TWI Data Register Bit 3 .equ TWD4 = 4 ; TWI Data Register Bit 4 .equ TWD5 = 5 ; TWI Data Register Bit 5 .equ TWD6 = 6 ; TWI Data Register Bit 6 .equ TWD7 = 7 ; TWI Data Register Bit 7 ; TWAR - TWI (Slave) Address register .equ TWGCE = 0 ; TWI General Call Recognition Enable Bit .equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 .equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 .equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 .equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 .equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 .equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 .equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 ; * LOCKSBITS **************************************************** .equ LB1 = 0 ; Lock bit .equ LB2 = 1 ; Lock bit .equ BLB01 = 2 ; Boot Lock bit .equ BLB02 = 3 ; Boot Lock bit .equ BLB11 = 4 ; Boot lock bit .equ BLB12 = 5 ; Boot lock bit ; * FUSES ******************************************************** ; LOW fuse bits .equ CKSEL0 = 0 ; Select Clock Source .equ CKSEL1 = 1 ; Select Clock Source .equ CKSEL2 = 2 ; Select Clock Source .equ CKSEL3 = 3 ; Select Clock Source .equ BODEN = 6 ; Brown out detector enable .equ BODLEVEL = 7 ; Brown out detector trigger level ; HIGH fuse bits .equ BOOTRST = 0 ; Select Reset Vector .equ BOOTSZ0 = 1 ; Select Boot Size .equ BOOTSZ1 = 2 ; Select Boot Size .equ EESAVE = 3 ; EEPROM memory is preserved through chip erase .equ SPIEN = 5 ; Enable Serial programming and Data Downloading .equ JTAGEN = 6 ; Enable JTAG .equ OCDEN = 7 ; Enable OCD ; * CPU REGISTER DEFINITIONS ************************************* .def XH = r27 .def XL = r26 .def YH = r29 .def YL = r28 .def ZH = r31 .def ZL = r30 ; * DATA MEMORY DECLARATIONS ************************************* .equ FLASHEND = 0x3fff ; Note: Word address .equ IOEND = 0x003f .equ SRAM_START = 0x0060 .equ SRAM_SIZE = 2048 .equ RAMEND = 0x085f .equ XRAMEND = 0x0000 .equ E2END = 0x03ff .equ EEPROMEND = 0x03ff .equ EEADRBITS = 10 #pragma AVRPART MEMORY PROG_FLASH 32768 #pragma AVRPART MEMORY EEPROM 1024 #pragma AVRPART MEMORY INT_SRAM SIZE 2048 #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 ; * BOOTLOADER DECLARATIONS ************************************** .equ NRWW_START_ADDR = 0x3800 .equ NRWW_STOP_ADDR = 0x3fff .equ RWW_START_ADDR = 0x0 .equ RWW_STOP_ADDR = 0x37ff .equ PAGESIZE = 64 .equ FIRSTBOOTSTART = 0x3f00 .equ SECONDBOOTSTART = 0x3e00 .equ THIRDBOOTSTART = 0x3c00 .equ FOURTHBOOTSTART = 0x3800 .equ SMALLBOOTSTART = FIRSTBOOTSTART .equ LARGEBOOTSTART = FOURTHBOOTSTART ; * INTERRUPT VECTORS ********************************************** .equ INT0addr = 0x0002 ; External Interrupt Request 0 .equ INT1addr = 0x0004 ; External Interrupt Request 1 .equ INT2addr = 0x0006 ; External Interrupt Request 2 .equ OC2addr = 0x0008 ; Timer/Counter2 Compare Match .equ OVF2addr = 0x000a ; Timer/Counter2 Overflow .equ ICP1addr = 0x000c ; Timer/Counter1 Capture Event .equ OC1Aaddr = 0x000e ; Timer/Counter1 Compare Match A .equ OC1Baddr = 0x0010 ; Timer/Counter1 Compare Match B .equ OVF1addr = 0x0012 ; Timer/Counter1 Overflow .equ OC0addr = 0x0014 ; Timer/Counter0 Compare Match .equ OVF0addr = 0x0016 ; Timer/Counter0 Overflow .equ SPIaddr = 0x0018 ; Serial Transfer Complete .equ URXCaddr = 0x001a ; USART, Rx Complete .equ UDREaddr = 0x001c ; USART Data Register Empty .equ UTXCaddr = 0x001e ; USART, Tx Complete .equ ADCCaddr = 0x0020 ; ADC Conversion Complete .equ ERDYaddr = 0x0022 ; EEPROM Ready .equ ACIaddr = 0x0024 ; Analog Comparator .equ TWIaddr = 0x0026 ; 2-wire Serial Interface .equ SPMRaddr = 0x0028 ; Store Program Memory Ready .equ INT_VECTORS_SIZE = 42 ; size in words #endif /* _M32DEF_INC_ / ; ** END OF FILE ****************************************************	/* Copyright (c) 2002, Steinar Haugen All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. / / $Id: iom32.h,v 1.11.2.6 2009/02/11 18:05:27 arcanum Exp $ / / avr/iom32.h - definitions for ATmega32 / #ifndef _AVR_IOM32_H_ #define _AVR_IOM32_H_ 1 / This file should only be included from <avr/io.h>, never directly. / #ifndef _AVR_IO_H_ # error "Include <avr/io.h> instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom32.h" #else # error "Attempt to include more than one <avr/ioXXX.h> file." #endif / I/O registers / / TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" / #define TWBR _SFR_IO8(0x00) #define TWSR _SFR_IO8(0x01) #define TWAR _SFR_IO8(0x02) #define TWDR _SFR_IO8(0x03) / ADC / #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCW _SFR_IO16(0x04) #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) #define ADCSRA _SFR_IO8(0x06) #define ADMUX _SFR_IO8(0x07) / analog comparator / #define ACSR _SFR_IO8(0x08) / USART / #define UBRRL _SFR_IO8(0x09) #define UCSRB _SFR_IO8(0x0A) #define UCSRA _SFR_IO8(0x0B) #define UDR _SFR_IO8(0x0C) / SPI / #define SPCR _SFR_IO8(0x0D) #define SPSR _SFR_IO8(0x0E) #define SPDR _SFR_IO8(0x0F) / Port D / #define PIND _SFR_IO8(0x10) #define DDRD _SFR_IO8(0x11) #define PORTD _SFR_IO8(0x12) / Port C / #define PINC _SFR_IO8(0x13) #define DDRC _SFR_IO8(0x14) #define PORTC _SFR_IO8(0x15) / Port B / #define PINB _SFR_IO8(0x16) #define DDRB _SFR_IO8(0x17) #define PORTB _SFR_IO8(0x18) / Port A / #define PINA _SFR_IO8(0x19) #define DDRA _SFR_IO8(0x1A) #define PORTA _SFR_IO8(0x1B) / EEPROM Control Register / #define EECR _SFR_IO8(0x1C) / EEPROM Data Register / #define EEDR _SFR_IO8(0x1D) / EEPROM Address Register / #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEARH _SFR_IO8(0x1F) #define UBRRH _SFR_IO8(0x20) #define UCSRC UBRRH #define WDTCR _SFR_IO8(0x21) #define ASSR _SFR_IO8(0x22) / Timer 2 / #define OCR2 _SFR_IO8(0x23) #define TCNT2 _SFR_IO8(0x24) #define TCCR2 _SFR_IO8(0x25) / Timer 1 / #define ICR1 _SFR_IO16(0x26) #define ICR1L _SFR_IO8(0x26) #define ICR1H _SFR_IO8(0x27) #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) #define TCCR1B _SFR_IO8(0x2E) #define TCCR1A _SFR_IO8(0x2F) #define SFIOR _SFR_IO8(0x30) #define OSCCAL _SFR_IO8(0x31) #define OCDR OSCCAL / Timer 0 / #define TCNT0 _SFR_IO8(0x32) #define TCCR0 _SFR_IO8(0x33) #define MCUSR _SFR_IO8(0x34) #define MCUCSR MCUSR #define MCUCR _SFR_IO8(0x35) #define TWCR _SFR_IO8(0x36) #define SPMCR _SFR_IO8(0x37) #define TIFR _SFR_IO8(0x38) #define TIMSK _SFR_IO8(0x39) #define GIFR _SFR_IO8(0x3A) #define GIMSK _SFR_IO8(0x3B) #define GICR GIMSK #define OCR0 _SFR_IO8(0x3C) / 0x3D..0x3E SP / / 0x3F SREG / / Interrupt vectors / / External Interrupt Request 0 / #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) / External Interrupt Request 1 / #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) / External Interrupt Request 2 / #define INT2_vect _VECTOR(3) #define SIG_INTERRUPT2 _VECTOR(3) / Timer/Counter2 Compare Match / #define TIMER2_COMP_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE2 _VECTOR(4) / Timer/Counter2 Overflow / #define TIMER2_OVF_vect _VECTOR(5) #define SIG_OVERFLOW2 _VECTOR(5) / Timer/Counter1 Capture Event / #define TIMER1_CAPT_vect _VECTOR(6) #define SIG_INPUT_CAPTURE1 _VECTOR(6) / Timer/Counter1 Compare Match A / #define TIMER1_COMPA_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1A _VECTOR(7) / Timer/Counter1 Compare Match B / #define TIMER1_COMPB_vect _VECTOR(8) #define SIG_OUTPUT_COMPARE1B _VECTOR(8) / Timer/Counter1 Overflow / #define TIMER1_OVF_vect _VECTOR(9) #define SIG_OVERFLOW1 _VECTOR(9) / Timer/Counter0 Compare Match / #define TIMER0_COMP_vect _VECTOR(10) #define SIG_OUTPUT_COMPARE0 _VECTOR(10) / Timer/Counter0 Overflow / #define TIMER0_OVF_vect _VECTOR(11) #define SIG_OVERFLOW0 _VECTOR(11) / Serial Transfer Complete / #define SPI_STC_vect _VECTOR(12) #define SIG_SPI _VECTOR(12) / USART, Rx Complete / #define USART_RXC_vect _VECTOR(13) #define SIG_USART_RECV _VECTOR(13) #define SIG_UART_RECV _VECTOR(13) / USART Data Register Empty / #define USART_UDRE_vect _VECTOR(14) #define SIG_USART_DATA _VECTOR(14) #define SIG_UART_DATA _VECTOR(14) / USART, Tx Complete / #define USART_TXC_vect _VECTOR(15) #define SIG_USART_TRANS _VECTOR(15) #define SIG_UART_TRANS _VECTOR(15) / ADC Conversion Complete / #define ADC_vect _VECTOR(16) #define SIG_ADC _VECTOR(16) / EEPROM Ready / #define EE_RDY_vect _VECTOR(17) #define SIG_EEPROM_READY _VECTOR(17) / Analog Comparator / #define ANA_COMP_vect _VECTOR(18) #define SIG_COMPARATOR _VECTOR(18) / 2-wire Serial Interface / #define TWI_vect _VECTOR(19) #define SIG_2WIRE_SERIAL _VECTOR(19) / Store Program Memory Ready / #define SPM_RDY_vect _VECTOR(20) #define SIG_SPM_READY _VECTOR(20) #define _VECTORS_SIZE 84 / Bit numbers / / GICR / #define INT1 7 #define INT0 6 #define INT2 5 #define IVSEL 1 #define IVCE 0 / GIFR / #define INTF1 7 #define INTF0 6 #define INTF2 5 / TIMSK / #define OCIE2 7 #define TOIE2 6 #define TICIE1 5 #define OCIE1A 4 #define OCIE1B 3 #define TOIE1 2 #define OCIE0 1 #define TOIE0 0 / TIFR / #define OCF2 7 #define TOV2 6 #define ICF1 5 #define OCF1A 4 #define OCF1B 3 #define TOV1 2 #define OCF0 1 #define TOV0 0 / SPMCR / #define SPMIE 7 #define RWWSB 6 / bit 5 reserved / #define RWWSRE 4 #define BLBSET 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 / TWCR / #define TWINT 7 #define TWEA 6 #define TWSTA 5 #define TWSTO 4 #define TWWC 3 #define TWEN 2 / bit 1 reserved / #define TWIE 0 / TWAR / #define TWA6 7 #define TWA5 6 #define TWA4 5 #define TWA3 4 #define TWA2 3 #define TWA1 2 #define TWA0 1 #define TWGCE 0 / TWSR / #define TWS7 7 #define TWS6 6 #define TWS5 5 #define TWS4 4 #define TWS3 3 / bit 2 reserved / #define TWPS1 1 #define TWPS0 0 / MCUCR / #define SE 7 #define SM2 6 #define SM1 5 #define SM0 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 / MCUCSR / #define JTD 7 #define ISC2 6 / bit 5 reserved / #define JTRF 4 #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 / SFIOR / #define ADTS2 7 #define ADTS1 6 #define ADTS0 5 / bit 4 reserved / #define ACME 3 #define PUD 2 #define PSR2 1 #define PSR10 0 / TCCR0 / #define FOC0 7 #define WGM00 6 #define COM01 5 #define COM00 4 #define WGM01 3 #define CS02 2 #define CS01 1 #define CS00 0 / TCCR2 / #define FOC2 7 #define WGM20 6 #define COM21 5 #define COM20 4 #define WGM21 3 #define CS22 2 #define CS21 1 #define CS20 0 / ASSR / / bits 7-4 reserved / #define AS2 3 #define TCN2UB 2 #define OCR2UB 1 #define TCR2UB 0 / TCCR1A / #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define FOC1A 3 #define FOC1B 2 #define WGM11 1 #define WGM10 0 / TCCR1B / #define ICNC1 7 #define ICES1 6 / bit 5 reserved / #define WGM13 4 #define WGM12 3 #define CS12 2 #define CS11 1 #define CS10 0 / WDTCR / / bits 7-5 reserved / #define WDTOE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 / PA7-PA0 = ADC7-ADC0 / / PORTA / #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 / DDRA / #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 / PINA / #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 / PB7 = SCK PB6 = MISO PB5 = MOSI PB4 = SS# PB3 = OC0/AIN1 PB2 = INT2/AIN0 PB1 = T1 PB0 = XCK/T0 / / PORTB / #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 / DDRB / #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 / PINB / #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 / PC7 = TOSC2 PC6 = TOSC1 PC1 = SDA PC0 = SCL / / PORTC / #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 / DDRC / #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 / PINC / #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 / PD7 = OC2 PD6 = ICP PD5 = OC1A PD4 = OC1B PD3 = INT1 PD2 = INT0 PD1 = TXD PD0 = RXD / / PORTD / #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 / DDRD / #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 / PIND / #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 / SPSR / #define SPIF 7 #define WCOL 6 / bits 5-1 reserved / #define SPI2X 0 / SPCR / #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 / UCSRA / #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 #define PE 2 #define U2X 1 #define MPCM 0 / UCSRB / #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define UCSZ2 2 #define RXB8 1 #define TXB8 0 / UCSRC / #define URSEL 7 #define UMSEL 6 #define UPM1 5 #define UPM0 4 #define USBS 3 #define UCSZ1 2 #define UCSZ0 1 #define UCPOL 0 / ACSR / #define ACD 7 #define ACBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 / ADCSRA / #define ADEN 7 #define ADSC 6 #define ADATE 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 / ADMUX / #define REFS1 7 #define REFS0 6 #define ADLAR 5 #define MUX4 4 #define MUX3 3 #define MUX2 2 #define MUX1 1 #define MUX0 0 / EEPROM Control Register / #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 / Constants / #define SPM_PAGESIZE 128 #define RAMEND 0x85F #define XRAMEND RAMEND #define E2END 0x3FF #define E2PAGESIZE 4 #define FLASHEND 0x7FFF / Fuses / #define FUSE_MEMORY_SIZE 2 / Low Fuse Byte / #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_BODEN (unsigned char)~_BV(6) #define FUSE_BODLEVEL (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) / High Fuse Byte / #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_CKOPT (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) / Lock Bits / #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST / Signature / #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x95 #define SIGNATURE_2 0x02 #endif / _AVR_IOM32_H_ */

ATmega48

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[m48def.inc] [iom48.h]

;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** ;***** Created: 2009-11-03 14:40 ******* Source: ATmega48.xml ************ ;************************************************************************* ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y ;* ;* Number : AVR000 ;* File Name : "m48def.inc" ;* Title : Register/Bit Definitions for the ATmega48 ;* Date : 2009-11-03 ;* Version : 2.35 ;* Support E-mail : avr@atmel.com ;* Target MCU : ATmega48 ;* ;* DESCRIPTION ;* When including this file in the assembly program file, all I/O register ;* names and I/O register bit names appearing in the data book can be used. ;* In addition, the six registers forming the three data pointers X, Y and ;* Z have been assigned names XL - ZH. Highest RAM address for Internal ;* SRAM is also defined ;* ;* The Register names are represented by their hexadecimal address. ;* ;* The Register Bit names are represented by their bit number (0-7). ;* ;* Please observe the difference in using the bit names with instructions ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" ;* (skip if bit in register set/cleared). The following example illustrates ;* this: ;* ;* in r16,PORTB ;read PORTB latch ;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) ;* out PORTB,r16 ;output to PORTB ;* ;* in r16,TIFR ;read the Timer Interrupt Flag Register ;* sbrc r16,TOV0 ;test the overflow flag (use bit#) ;* rjmp TOV0_is_set ;jump if set ;* ... ;otherwise do something else ;************************************************************************* #ifndef _M48DEF_INC_ #define _M48DEF_INC_ #pragma partinc 0 ; ***** SPECIFY DEVICE *************************************************** .device ATmega48 #pragma AVRPART ADMIN PART_NAME ATmega48 .equ SIGNATURE_000 = 0x1e .equ SIGNATURE_001 = 0x92 .equ SIGNATURE_002 = 0x05 #pragma AVRPART CORE CORE_VERSION V2E ; ***** I/O REGISTER DEFINITIONS ***************************************** ; NOTE: ; Definitions marked "MEMORY MAPPED"are extended I/O ports ; and cannot be used with IN/OUT instructions .equ UDR0 = 0xc6 ; MEMORY MAPPED .equ UBRR0L = 0xc4 ; MEMORY MAPPED .equ UBRR0H = 0xc5 ; MEMORY MAPPED .equ UCSR0C = 0xc2 ; MEMORY MAPPED .equ UCSR0B = 0xc1 ; MEMORY MAPPED .equ UCSR0A = 0xc0 ; MEMORY MAPPED .equ TWAMR = 0xbd ; MEMORY MAPPED .equ TWCR = 0xbc ; MEMORY MAPPED .equ TWDR = 0xbb ; MEMORY MAPPED .equ TWAR = 0xba ; MEMORY MAPPED .equ TWSR = 0xb9 ; MEMORY MAPPED .equ TWBR = 0xb8 ; MEMORY MAPPED .equ ASSR = 0xb6 ; MEMORY MAPPED .equ OCR2B = 0xb4 ; MEMORY MAPPED .equ OCR2A = 0xb3 ; MEMORY MAPPED .equ TCNT2 = 0xb2 ; MEMORY MAPPED .equ TCCR2B = 0xb1 ; MEMORY MAPPED .equ TCCR2A = 0xb0 ; MEMORY MAPPED .equ OCR1BL = 0x8a ; MEMORY MAPPED .equ OCR1BH = 0x8b ; MEMORY MAPPED .equ OCR1AL = 0x88 ; MEMORY MAPPED .equ OCR1AH = 0x89 ; MEMORY MAPPED .equ ICR1L = 0x86 ; MEMORY MAPPED .equ ICR1H = 0x87 ; MEMORY MAPPED .equ TCNT1L = 0x84 ; MEMORY MAPPED .equ TCNT1H = 0x85 ; MEMORY MAPPED .equ TCCR1C = 0x82 ; MEMORY MAPPED .equ TCCR1B = 0x81 ; MEMORY MAPPED .equ TCCR1A = 0x80 ; MEMORY MAPPED .equ DIDR1 = 0x7f ; MEMORY MAPPED .equ DIDR0 = 0x7e ; MEMORY MAPPED .equ ADMUX = 0x7c ; MEMORY MAPPED .equ ADCSRB = 0x7b ; MEMORY MAPPED .equ ADCSRA = 0x7a ; MEMORY MAPPED .equ ADCH = 0x79 ; MEMORY MAPPED .equ ADCL = 0x78 ; MEMORY MAPPED .equ TIMSK2 = 0x70 ; MEMORY MAPPED .equ TIMSK1 = 0x6f ; MEMORY MAPPED .equ TIMSK0 = 0x6e ; MEMORY MAPPED .equ PCMSK1 = 0x6c ; MEMORY MAPPED .equ PCMSK2 = 0x6d ; MEMORY MAPPED .equ PCMSK0 = 0x6b ; MEMORY MAPPED .equ EICRA = 0x69 ; MEMORY MAPPED .equ PCICR = 0x68 ; MEMORY MAPPED .equ OSCCAL = 0x66 ; MEMORY MAPPED .equ PRR = 0x64 ; MEMORY MAPPED .equ CLKPR = 0x61 ; MEMORY MAPPED .equ WDTCSR = 0x60 ; MEMORY MAPPED .equ SREG = 0x3f .equ SPL = 0x3d .equ SPH = 0x3e .equ SPMCSR = 0x37 .equ MCUCR = 0x35 .equ MCUSR = 0x34 .equ SMCR = 0x33 .equ ACSR = 0x30 .equ SPDR = 0x2e .equ SPSR = 0x2d .equ SPCR = 0x2c .equ GPIOR2 = 0x2b .equ GPIOR1 = 0x2a .equ OCR0B = 0x28 .equ OCR0A = 0x27 .equ TCNT0 = 0x26 .equ TCCR0B = 0x25 .equ TCCR0A = 0x24 .equ GTCCR = 0x23 .equ EEARL = 0x21 .equ EEDR = 0x20 .equ EECR = 0x1f .equ GPIOR0 = 0x1e .equ EIMSK = 0x1d .equ EIFR = 0x1c .equ PCIFR = 0x1b .equ TIFR2 = 0x17 .equ TIFR1 = 0x16 .equ TIFR0 = 0x15 .equ PORTD = 0x0b .equ DDRD = 0x0a .equ PIND = 0x09 .equ PORTC = 0x08 .equ DDRC = 0x07 .equ PINC = 0x06 .equ PORTB = 0x05 .equ DDRB = 0x04 .equ PINB = 0x03 ; ***** BIT DEFINITIONS ************************************************** ; ***** USART0 *********************** ; UDR0 - USART I/O Data Register .equ UDR0_0 = 0 ; USART I/O Data Register bit 0 .equ UDR0_1 = 1 ; USART I/O Data Register bit 1 .equ UDR0_2 = 2 ; USART I/O Data Register bit 2 .equ UDR0_3 = 3 ; USART I/O Data Register bit 3 .equ UDR0_4 = 4 ; USART I/O Data Register bit 4 .equ UDR0_5 = 5 ; USART I/O Data Register bit 5 .equ UDR0_6 = 6 ; USART I/O Data Register bit 6 .equ UDR0_7 = 7 ; USART I/O Data Register bit 7 ; UCSR0A - USART Control and Status Register A .equ MPCM0 = 0 ; Multi-processor Communication Mode .equ U2X0 = 1 ; Double the USART transmission speed .equ UPE0 = 2 ; Parity Error .equ DOR0 = 3 ; Data overRun .equ FE0 = 4 ; Framing Error .equ UDRE0 = 5 ; USART Data Register Empty .equ TXC0 = 6 ; USART Transmitt Complete .equ RXC0 = 7 ; USART Receive Complete ; UCSR0B - USART Control and Status Register B .equ TXB80 = 0 ; Transmit Data Bit 8 .equ RXB80 = 1 ; Receive Data Bit 8 .equ UCSZ02 = 2 ; Character Size .equ TXEN0 = 3 ; Transmitter Enable .equ RXEN0 = 4 ; Receiver Enable .equ UDRIE0 = 5 ; USART Data register Empty Interrupt Enable .equ TXCIE0 = 6 ; TX Complete Interrupt Enable .equ RXCIE0 = 7 ; RX Complete Interrupt Enable ; UCSR0C - USART Control and Status Register C .equ UCPOL0 = 0 ; Clock Polarity .equ UCSZ00 = 1 ; Character Size .equ UCPHA0 = UCSZ00 ; For compatibility .equ UCSZ01 = 2 ; Character Size .equ UDORD0 = UCSZ01 ; For compatibility .equ USBS0 = 3 ; Stop Bit Select .equ UPM00 = 4 ; Parity Mode Bit 0 .equ UPM01 = 5 ; Parity Mode Bit 1 .equ UMSEL00 = 6 ; USART Mode Select .equ UMSEL0 = UMSEL00 ; For compatibility .equ UMSEL01 = 7 ; USART Mode Select .equ UMSEL1 = UMSEL01 ; For compatibility ; UBRR0H - USART Baud Rate Register High Byte .equ UBRR8 = 0 ; USART Baud Rate Register bit 8 .equ UBRR9 = 1 ; USART Baud Rate Register bit 9 .equ UBRR10 = 2 ; USART Baud Rate Register bit 10 .equ UBRR11 = 3 ; USART Baud Rate Register bit 11 ; UBRR0L - USART Baud Rate Register Low Byte .equ _UBRR0 = 0 ; USART Baud Rate Register bit 0 .equ _UBRR1 = 1 ; USART Baud Rate Register bit 1 .equ UBRR2 = 2 ; USART Baud Rate Register bit 2 .equ UBRR3 = 3 ; USART Baud Rate Register bit 3 .equ UBRR4 = 4 ; USART Baud Rate Register bit 4 .equ UBRR5 = 5 ; USART Baud Rate Register bit 5 .equ UBRR6 = 6 ; USART Baud Rate Register bit 6 .equ UBRR7 = 7 ; USART Baud Rate Register bit 7 ; ***** TWI ************************** ; TWAMR - TWI (Slave) Address Mask Register .equ TWAM0 = 1 ; .equ TWAMR0 = TWAM0 ; For compatibility .equ TWAM1 = 2 ; .equ TWAMR1 = TWAM1 ; For compatibility .equ TWAM2 = 3 ; .equ TWAMR2 = TWAM2 ; For compatibility .equ TWAM3 = 4 ; .equ TWAMR3 = TWAM3 ; For compatibility .equ TWAM4 = 5 ; .equ TWAMR4 = TWAM4 ; For compatibility .equ TWAM5 = 6 ; .equ TWAMR5 = TWAM5 ; For compatibility .equ TWAM6 = 7 ; .equ TWAMR6 = TWAM6 ; For compatibility ; TWBR - TWI Bit Rate register .equ TWBR0 = 0 ; .equ TWBR1 = 1 ; .equ TWBR2 = 2 ; .equ TWBR3 = 3 ; .equ TWBR4 = 4 ; .equ TWBR5 = 5 ; .equ TWBR6 = 6 ; .equ TWBR7 = 7 ; ; TWCR - TWI Control Register .equ TWIE = 0 ; TWI Interrupt Enable .equ TWEN = 2 ; TWI Enable Bit .equ TWWC = 3 ; TWI Write Collition Flag .equ TWSTO = 4 ; TWI Stop Condition Bit .equ TWSTA = 5 ; TWI Start Condition Bit .equ TWEA = 6 ; TWI Enable Acknowledge Bit .equ TWINT = 7 ; TWI Interrupt Flag ; TWSR - TWI Status Register .equ TWPS0 = 0 ; TWI Prescaler .equ TWPS1 = 1 ; TWI Prescaler .equ TWS3 = 3 ; TWI Status .equ TWS4 = 4 ; TWI Status .equ TWS5 = 5 ; TWI Status .equ TWS6 = 6 ; TWI Status .equ TWS7 = 7 ; TWI Status ; TWDR - TWI Data register .equ TWD0 = 0 ; TWI Data Register Bit 0 .equ TWD1 = 1 ; TWI Data Register Bit 1 .equ TWD2 = 2 ; TWI Data Register Bit 2 .equ TWD3 = 3 ; TWI Data Register Bit 3 .equ TWD4 = 4 ; TWI Data Register Bit 4 .equ TWD5 = 5 ; TWI Data Register Bit 5 .equ TWD6 = 6 ; TWI Data Register Bit 6 .equ TWD7 = 7 ; TWI Data Register Bit 7 ; TWAR - TWI (Slave) Address register .equ TWGCE = 0 ; TWI General Call Recognition Enable Bit .equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 .equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 .equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 .equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 .equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 .equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 .equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 ; ***** TIMER_COUNTER_1 ************** ; TIMSK1 - Timer/Counter Interrupt Mask Register .equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable .equ OCIE1A = 1 ; Timer/Counter1 Output CompareA Match Interrupt Enable .equ OCIE1B = 2 ; Timer/Counter1 Output CompareB Match Interrupt Enable .equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable ; TIFR1 - Timer/Counter Interrupt Flag register .equ TOV1 = 0 ; Timer/Counter1 Overflow Flag .equ OCF1A = 1 ; Output Compare Flag 1A .equ OCF1B = 2 ; Output Compare Flag 1B .equ ICF1 = 5 ; Input Capture Flag 1 ; TCCR1A - Timer/Counter1 Control Register A .equ WGM10 = 0 ; Waveform Generation Mode .equ WGM11 = 1 ; Waveform Generation Mode .equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 .equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 .equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0 .equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 ; TCCR1B - Timer/Counter1 Control Register B .equ CS10 = 0 ; Prescaler source of Timer/Counter 1 .equ CS11 = 1 ; Prescaler source of Timer/Counter 1 .equ CS12 = 2 ; Prescaler source of Timer/Counter 1 .equ WGM12 = 3 ; Waveform Generation Mode .equ WGM13 = 4 ; Waveform Generation Mode .equ ICES1 = 6 ; Input Capture 1 Edge Select .equ ICNC1 = 7 ; Input Capture 1 Noise Canceler ; TCCR1C - Timer/Counter1 Control Register C .equ FOC1B = 6 ; .equ FOC1A = 7 ; ; GTCCR - General Timer/Counter Control Register .equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 .equ TSM = 7 ; Timer/Counter Synchronization Mode ; ***** TIMER_COUNTER_2 ************** ; TIMSK2 - Timer/Counter Interrupt Mask register .equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable .equ TOIE2A = TOIE2 ; For compatibility .equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match A Interrupt Enable .equ OCIE2B = 2 ; Timer/Counter2 Output Compare Match B Interrupt Enable ; TIFR2 - Timer/Counter Interrupt Flag Register .equ TOV2 = 0 ; Timer/Counter2 Overflow Flag .equ OCF2A = 1 ; Output Compare Flag 2A .equ OCF2B = 2 ; Output Compare Flag 2B ; TCCR2A - Timer/Counter2 Control Register A .equ WGM20 = 0 ; Waveform Genration Mode .equ WGM21 = 1 ; Waveform Genration Mode .equ COM2B0 = 4 ; Compare Output Mode bit 0 .equ COM2B1 = 5 ; Compare Output Mode bit 1 .equ COM2A0 = 6 ; Compare Output Mode bit 1 .equ COM2A1 = 7 ; Compare Output Mode bit 1 ; TCCR2B - Timer/Counter2 Control Register B .equ CS20 = 0 ; Clock Select bit 0 .equ CS21 = 1 ; Clock Select bit 1 .equ CS22 = 2 ; Clock Select bit 2 .equ WGM22 = 3 ; Waveform Generation Mode .equ FOC2B = 6 ; Force Output Compare B .equ FOC2A = 7 ; Force Output Compare A ; TCNT2 - Timer/Counter2 .equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 .equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 .equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 .equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 .equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 .equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 .equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 .equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 ; OCR2A - Timer/Counter2 Output Compare Register A .equ OCR2A_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 .equ OCR2A_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 .equ OCR2A_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 .equ OCR2A_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 .equ OCR2A_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 .equ OCR2A_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 .equ OCR2A_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 .equ OCR2A_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 ; OCR2B - Timer/Counter2 Output Compare Register B .equ OCR2B_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 .equ OCR2B_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 .equ OCR2B_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 .equ OCR2B_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 .equ OCR2B_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 .equ OCR2B_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 .equ OCR2B_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 .equ OCR2B_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 ; ASSR - Asynchronous Status Register .equ TCR2BUB = 0 ; Timer/Counter Control Register2 Update Busy .equ TCR2AUB = 1 ; Timer/Counter Control Register2 Update Busy .equ OCR2BUB = 2 ; Output Compare Register 2 Update Busy .equ OCR2AUB = 3 ; Output Compare Register2 Update Busy .equ TCN2UB = 4 ; Timer/Counter2 Update Busy .equ AS2 = 5 ; Asynchronous Timer/Counter2 .equ EXCLK = 6 ; Enable External Clock Input ; GTCCR - General Timer Counter Control register .equ PSRASY = 1 ; Prescaler Reset Timer/Counter2 .equ PSR2 = PSRASY ; For compatibility ;.equ TSM = 7 ; Timer/Counter Synchronization Mode ; ***** AD_CONVERTER ***************** ; ADMUX - The ADC multiplexer Selection Register .equ MUX0 = 0 ; Analog Channel and Gain Selection Bits .equ MUX1 = 1 ; Analog Channel and Gain Selection Bits .equ MUX2 = 2 ; Analog Channel and Gain Selection Bits .equ MUX3 = 3 ; Analog Channel and Gain Selection Bits .equ ADLAR = 5 ; Left Adjust Result .equ REFS0 = 6 ; Reference Selection Bit 0 .equ REFS1 = 7 ; Reference Selection Bit 1 ; ADCSRA - The ADC Control and Status register A .equ ADPS0 = 0 ; ADC Prescaler Select Bits .equ ADPS1 = 1 ; ADC Prescaler Select Bits .equ ADPS2 = 2 ; ADC Prescaler Select Bits .equ ADIE = 3 ; ADC Interrupt Enable .equ ADIF = 4 ; ADC Interrupt Flag .equ ADATE = 5 ; ADC Auto Trigger Enable .equ ADSC = 6 ; ADC Start Conversion .equ ADEN = 7 ; ADC Enable ; ADCSRB - The ADC Control and Status register B .equ ADTS0 = 0 ; ADC Auto Trigger Source bit 0 .equ ADTS1 = 1 ; ADC Auto Trigger Source bit 1 .equ ADTS2 = 2 ; ADC Auto Trigger Source bit 2 .equ ACME = 6 ; ; ADCH - ADC Data Register High Byte .equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 .equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 .equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 .equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 .equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 .equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 .equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 .equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 ; ADCL - ADC Data Register Low Byte .equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 .equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 .equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 .equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 .equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 .equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 .equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 .equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 ; DIDR0 - Digital Input Disable Register .equ ADC0D = 0 ; .equ ADC1D = 1 ; .equ ADC2D = 2 ; .equ ADC3D = 3 ; .equ ADC4D = 4 ; .equ ADC5D = 5 ; ; ***** ANALOG_COMPARATOR ************ ; ACSR - Analog Comparator Control And Status Register .equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 .equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 .equ ACIC = 2 ; Analog Comparator Input Capture Enable .equ ACIE = 3 ; Analog Comparator Interrupt Enable .equ ACI = 4 ; Analog Comparator Interrupt Flag .equ ACO = 5 ; Analog Compare Output .equ ACBG = 6 ; Analog Comparator Bandgap Select .equ ACD = 7 ; Analog Comparator Disable ; DIDR1 - Digital Input Disable Register 1 .equ AIN0D = 0 ; AIN0 Digital Input Disable .equ AIN1D = 1 ; AIN1 Digital Input Disable ; ***** PORTB ************************ ; PORTB - Port B Data Register .equ PORTB0 = 0 ; Port B Data Register bit 0 .equ PB0 = 0 ; For compatibility .equ PORTB1 = 1 ; Port B Data Register bit 1 .equ PB1 = 1 ; For compatibility .equ PORTB2 = 2 ; Port B Data Register bit 2 .equ PB2 = 2 ; For compatibility .equ PORTB3 = 3 ; Port B Data Register bit 3 .equ PB3 = 3 ; For compatibility .equ PORTB4 = 4 ; Port B Data Register bit 4 .equ PB4 = 4 ; For compatibility .equ PORTB5 = 5 ; Port B Data Register bit 5 .equ PB5 = 5 ; For compatibility .equ PORTB6 = 6 ; Port B Data Register bit 6 .equ PB6 = 6 ; For compatibility .equ PORTB7 = 7 ; Port B Data Register bit 7 .equ PB7 = 7 ; For compatibility ; DDRB - Port B Data Direction Register .equ DDB0 = 0 ; Port B Data Direction Register bit 0 .equ DDB1 = 1 ; Port B Data Direction Register bit 1 .equ DDB2 = 2 ; Port B Data Direction Register bit 2 .equ DDB3 = 3 ; Port B Data Direction Register bit 3 .equ DDB4 = 4 ; Port B Data Direction Register bit 4 .equ DDB5 = 5 ; Port B Data Direction Register bit 5 .equ DDB6 = 6 ; Port B Data Direction Register bit 6 .equ DDB7 = 7 ; Port B Data Direction Register bit 7 ; PINB - Port B Input Pins .equ PINB0 = 0 ; Port B Input Pins bit 0 .equ PINB1 = 1 ; Port B Input Pins bit 1 .equ PINB2 = 2 ; Port B Input Pins bit 2 .equ PINB3 = 3 ; Port B Input Pins bit 3 .equ PINB4 = 4 ; Port B Input Pins bit 4 .equ PINB5 = 5 ; Port B Input Pins bit 5 .equ PINB6 = 6 ; Port B Input Pins bit 6 .equ PINB7 = 7 ; Port B Input Pins bit 7 ; ***** PORTC ************************ ; PORTC - Port C Data Register .equ PORTC0 = 0 ; Port C Data Register bit 0 .equ PC0 = 0 ; For compatibility .equ PORTC1 = 1 ; Port C Data Register bit 1 .equ PC1 = 1 ; For compatibility .equ PORTC2 = 2 ; Port C Data Register bit 2 .equ PC2 = 2 ; For compatibility .equ PORTC3 = 3 ; Port C Data Register bit 3 .equ PC3 = 3 ; For compatibility .equ PORTC4 = 4 ; Port C Data Register bit 4 .equ PC4 = 4 ; For compatibility .equ PORTC5 = 5 ; Port C Data Register bit 5 .equ PC5 = 5 ; For compatibility .equ PORTC6 = 6 ; Port C Data Register bit 6 .equ PC6 = 6 ; For compatibility ; DDRC - Port C Data Direction Register .equ DDC0 = 0 ; Port C Data Direction Register bit 0 .equ DDC1 = 1 ; Port C Data Direction Register bit 1 .equ DDC2 = 2 ; Port C Data Direction Register bit 2 .equ DDC3 = 3 ; Port C Data Direction Register bit 3 .equ DDC4 = 4 ; Port C Data Direction Register bit 4 .equ DDC5 = 5 ; Port C Data Direction Register bit 5 .equ DDC6 = 6 ; Port C Data Direction Register bit 6 ; PINC - Port C Input Pins .equ PINC0 = 0 ; Port C Input Pins bit 0 .equ PINC1 = 1 ; Port C Input Pins bit 1 .equ PINC2 = 2 ; Port C Input Pins bit 2 .equ PINC3 = 3 ; Port C Input Pins bit 3 .equ PINC4 = 4 ; Port C Input Pins bit 4 .equ PINC5 = 5 ; Port C Input Pins bit 5 .equ PINC6 = 6 ; Port C Input Pins bit 6 ; ***** PORTD ************************ ; PORTD - Port D Data Register .equ PORTD0 = 0 ; Port D Data Register bit 0 .equ PD0 = 0 ; For compatibility .equ PORTD1 = 1 ; Port D Data Register bit 1 .equ PD1 = 1 ; For compatibility .equ PORTD2 = 2 ; Port D Data Register bit 2 .equ PD2 = 2 ; For compatibility .equ PORTD3 = 3 ; Port D Data Register bit 3 .equ PD3 = 3 ; For compatibility .equ PORTD4 = 4 ; Port D Data Register bit 4 .equ PD4 = 4 ; For compatibility .equ PORTD5 = 5 ; Port D Data Register bit 5 .equ PD5 = 5 ; For compatibility .equ PORTD6 = 6 ; Port D Data Register bit 6 .equ PD6 = 6 ; For compatibility .equ PORTD7 = 7 ; Port D Data Register bit 7 .equ PD7 = 7 ; For compatibility ; DDRD - Port D Data Direction Register .equ DDD0 = 0 ; Port D Data Direction Register bit 0 .equ DDD1 = 1 ; Port D Data Direction Register bit 1 .equ DDD2 = 2 ; Port D Data Direction Register bit 2 .equ DDD3 = 3 ; Port D Data Direction Register bit 3 .equ DDD4 = 4 ; Port D Data Direction Register bit 4 .equ DDD5 = 5 ; Port D Data Direction Register bit 5 .equ DDD6 = 6 ; Port D Data Direction Register bit 6 .equ DDD7 = 7 ; Port D Data Direction Register bit 7 ; PIND - Port D Input Pins .equ PIND0 = 0 ; Port D Input Pins bit 0 .equ PIND1 = 1 ; Port D Input Pins bit 1 .equ PIND2 = 2 ; Port D Input Pins bit 2 .equ PIND3 = 3 ; Port D Input Pins bit 3 .equ PIND4 = 4 ; Port D Input Pins bit 4 .equ PIND5 = 5 ; Port D Input Pins bit 5 .equ PIND6 = 6 ; Port D Input Pins bit 6 .equ PIND7 = 7 ; Port D Input Pins bit 7 ; ***** TIMER_COUNTER_0 ************** ; TIMSK0 - Timer/Counter0 Interrupt Mask Register .equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable .equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable .equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable ; TIFR0 - Timer/Counter0 Interrupt Flag register .equ TOV0 = 0 ; Timer/Counter0 Overflow Flag .equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0A .equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B ; TCCR0A - Timer/Counter Control Register A .equ WGM00 = 0 ; Waveform Generation Mode .equ WGM01 = 1 ; Waveform Generation Mode .equ COM0B0 = 4 ; Compare Output Mode, Fast PWm .equ COM0B1 = 5 ; Compare Output Mode, Fast PWm .equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode .equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode ; TCCR0B - Timer/Counter Control Register B .equ CS00 = 0 ; Clock Select .equ CS01 = 1 ; Clock Select .equ CS02 = 2 ; Clock Select .equ WGM02 = 3 ; .equ FOC0B = 6 ; Force Output Compare B .equ FOC0A = 7 ; Force Output Compare A ; TCNT0 - Timer/Counter0 .equ TCNT0_0 = 0 ; .equ TCNT0_1 = 1 ; .equ TCNT0_2 = 2 ; .equ TCNT0_3 = 3 ; .equ TCNT0_4 = 4 ; .equ TCNT0_5 = 5 ; .equ TCNT0_6 = 6 ; .equ TCNT0_7 = 7 ; ; OCR0A - Timer/Counter0 Output Compare Register .equ OCR0A_0 = 0 ; .equ OCR0A_1 = 1 ; .equ OCR0A_2 = 2 ; .equ OCR0A_3 = 3 ; .equ OCR0A_4 = 4 ; .equ OCR0A_5 = 5 ; .equ OCR0A_6 = 6 ; .equ OCR0A_7 = 7 ; ; OCR0B - Timer/Counter0 Output Compare Register .equ OCR0B_0 = 0 ; .equ OCR0B_1 = 1 ; .equ OCR0B_2 = 2 ; .equ OCR0B_3 = 3 ; .equ OCR0B_4 = 4 ; .equ OCR0B_5 = 5 ; .equ OCR0B_6 = 6 ; .equ OCR0B_7 = 7 ; ; GTCCR - General Timer/Counter Control Register ;.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 .equ PSR10 = PSRSYNC ; For compatibility ;.equ TSM = 7 ; Timer/Counter Synchronization Mode ; ***** EXTERNAL_INTERRUPT *********** ; EICRA - External Interrupt Control Register .equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0 .equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1 .equ ISC10 = 2 ; External Interrupt Sense Control 1 Bit 0 .equ ISC11 = 3 ; External Interrupt Sense Control 1 Bit 1 ; EIMSK - External Interrupt Mask Register .equ INT0 = 0 ; External Interrupt Request 0 Enable .equ INT1 = 1 ; External Interrupt Request 1 Enable ; EIFR - External Interrupt Flag Register .equ INTF0 = 0 ; External Interrupt Flag 0 .equ INTF1 = 1 ; External Interrupt Flag 1 ; PCICR - Pin Change Interrupt Control Register .equ PCIE0 = 0 ; Pin Change Interrupt Enable 0 .equ PCIE1 = 1 ; Pin Change Interrupt Enable 1 .equ PCIE2 = 2 ; Pin Change Interrupt Enable 2 ; PCMSK2 - Pin Change Mask Register 2 .equ PCINT16 = 0 ; Pin Change Enable Mask 16 .equ PCINT17 = 1 ; Pin Change Enable Mask 17 .equ PCINT18 = 2 ; Pin Change Enable Mask 18 .equ PCINT19 = 3 ; Pin Change Enable Mask 19 .equ PCINT20 = 4 ; Pin Change Enable Mask 20 .equ PCINT21 = 5 ; Pin Change Enable Mask 21 .equ PCINT22 = 6 ; Pin Change Enable Mask 22 .equ PCINT23 = 7 ; Pin Change Enable Mask 23 ; PCMSK1 - Pin Change Mask Register 1 .equ PCINT8 = 0 ; Pin Change Enable Mask 8 .equ PCINT9 = 1 ; Pin Change Enable Mask 9 .equ PCINT10 = 2 ; Pin Change Enable Mask 10 .equ PCINT11 = 3 ; Pin Change Enable Mask 11 .equ PCINT12 = 4 ; Pin Change Enable Mask 12 .equ PCINT13 = 5 ; Pin Change Enable Mask 13 .equ PCINT14 = 6 ; Pin Change Enable Mask 14 ; PCMSK0 - Pin Change Mask Register 0 .equ PCINT0 = 0 ; Pin Change Enable Mask 0 .equ PCINT1 = 1 ; Pin Change Enable Mask 1 .equ PCINT2 = 2 ; Pin Change Enable Mask 2 .equ PCINT3 = 3 ; Pin Change Enable Mask 3 .equ PCINT4 = 4 ; Pin Change Enable Mask 4 .equ PCINT5 = 5 ; Pin Change Enable Mask 5 .equ PCINT6 = 6 ; Pin Change Enable Mask 6 .equ PCINT7 = 7 ; Pin Change Enable Mask 7 ; PCIFR - Pin Change Interrupt Flag Register .equ PCIF0 = 0 ; Pin Change Interrupt Flag 0 .equ PCIF1 = 1 ; Pin Change Interrupt Flag 1 .equ PCIF2 = 2 ; Pin Change Interrupt Flag 2 ; ***** SPI ************************** ; SPDR - SPI Data Register .equ SPDR0 = 0 ; SPI Data Register bit 0 .equ SPDR1 = 1 ; SPI Data Register bit 1 .equ SPDR2 = 2 ; SPI Data Register bit 2 .equ SPDR3 = 3 ; SPI Data Register bit 3 .equ SPDR4 = 4 ; SPI Data Register bit 4 .equ SPDR5 = 5 ; SPI Data Register bit 5 .equ SPDR6 = 6 ; SPI Data Register bit 6 .equ SPDR7 = 7 ; SPI Data Register bit 7 ; SPSR - SPI Status Register .equ SPI2X = 0 ; Double SPI Speed Bit .equ WCOL = 6 ; Write Collision Flag .equ SPIF = 7 ; SPI Interrupt Flag ; SPCR - SPI Control Register .equ SPR0 = 0 ; SPI Clock Rate Select 0 .equ SPR1 = 1 ; SPI Clock Rate Select 1 .equ CPHA = 2 ; Clock Phase .equ CPOL = 3 ; Clock polarity .equ MSTR = 4 ; Master/Slave Select .equ DORD = 5 ; Data Order .equ SPE = 6 ; SPI Enable .equ SPIE = 7 ; SPI Interrupt Enable ; ***** CPU ************************** ; SREG - Status Register .equ SREG_C = 0 ; Carry Flag .equ SREG_Z = 1 ; Zero Flag .equ SREG_N = 2 ; Negative Flag .equ SREG_V = 3 ; Two's Complement Overflow Flag .equ SREG_S = 4 ; Sign Bit .equ SREG_H = 5 ; Half Carry Flag .equ SREG_T = 6 ; Bit Copy Storage .equ SREG_I = 7 ; Global Interrupt Enable ; OSCCAL - Oscillator Calibration Value .equ CAL0 = 0 ; Oscillator Calibration Value Bit0 .equ CAL1 = 1 ; Oscillator Calibration Value Bit1 .equ CAL2 = 2 ; Oscillator Calibration Value Bit2 .equ CAL3 = 3 ; Oscillator Calibration Value Bit3 .equ CAL4 = 4 ; Oscillator Calibration Value Bit4 .equ CAL5 = 5 ; Oscillator Calibration Value Bit5 .equ CAL6 = 6 ; Oscillator Calibration Value Bit6 .equ CAL7 = 7 ; Oscillator Calibration Value Bit7 ; CLKPR - Clock Prescale Register .equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 .equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 .equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 .equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 .equ CLKPCE = 7 ; Clock Prescaler Change Enable ; SPMCSR - Store Program Memory Control Register .equ SELFPRGEN = 0 ; Self Programming Enable .equ PGERS = 1 ; Page Erase .equ PGWRT = 2 ; Page Write .equ BLBSET = 3 ; Boot Lock Bit Set .equ RWWSRE = 4 ; Read-While-Write section read enable .equ RWWSB = 6 ; Read-While-Write Section Busy .equ SPMIE = 7 ; SPM Interrupt Enable ; MCUCR - MCU Control Register .equ PUD = 4 ; ; MCUSR - MCU Status Register .equ PORF = 0 ; Power-on reset flag .equ EXTRF = 1 ; External Reset Flag .equ EXTREF = EXTRF ; For compatibility .equ BORF = 2 ; Brown-out Reset Flag .equ WDRF = 3 ; Watchdog Reset Flag ; SMCR - .equ SE = 0 ; .equ SM0 = 1 ; .equ SM1 = 2 ; .equ SM2 = 3 ; ; GPIOR2 - General Purpose I/O Register 2 .equ GPIOR20 = 0 ; .equ GPIOR21 = 1 ; .equ GPIOR22 = 2 ; .equ GPIOR23 = 3 ; .equ GPIOR24 = 4 ; .equ GPIOR25 = 5 ; .equ GPIOR26 = 6 ; .equ GPIOR27 = 7 ; ; GPIOR1 - General Purpose I/O Register 1 .equ GPIOR10 = 0 ; .equ GPIOR11 = 1 ; .equ GPIOR12 = 2 ; .equ GPIOR13 = 3 ; .equ GPIOR14 = 4 ; .equ GPIOR15 = 5 ; .equ GPIOR16 = 6 ; .equ GPIOR17 = 7 ; ; GPIOR0 - General Purpose I/O Register 0 .equ GPIOR00 = 0 ; .equ GPIOR01 = 1 ; .equ GPIOR02 = 2 ; .equ GPIOR03 = 3 ; .equ GPIOR04 = 4 ; .equ GPIOR05 = 5 ; .equ GPIOR06 = 6 ; .equ GPIOR07 = 7 ; ; PRR - Power Reduction Register .equ PRADC = 0 ; Power Reduction ADC .equ PRUSART0 = 1 ; Power Reduction USART .equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface .equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 .equ PRTIM0 = 5 ; Power Reduction Timer/Counter0 .equ PRTIM2 = 6 ; Power Reduction Timer/Counter2 .equ PRTWI = 7 ; Power Reduction TWI ; ***** WATCHDOG ********************* ; WDTCSR - Watchdog Timer Control Register .equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 .equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 .equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 .equ WDE = 3 ; Watch Dog Enable .equ WDCE = 4 ; Watchdog Change Enable .equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3 .equ WDIE = 6 ; Watchdog Timeout Interrupt Enable .equ WDIF = 7 ; Watchdog Timeout Interrupt Flag ; ***** EEPROM *********************** ; EEARL - EEPROM Address Register Low Byte .equ EEAR0 = 0 ; EEPROM Read/Write Access Bit 0 .equ EEAR1 = 1 ; EEPROM Read/Write Access Bit 1 .equ EEAR2 = 2 ; EEPROM Read/Write Access Bit 2 .equ EEAR3 = 3 ; EEPROM Read/Write Access Bit 3 .equ EEAR4 = 4 ; EEPROM Read/Write Access Bit 4 .equ EEAR5 = 5 ; EEPROM Read/Write Access Bit 5 .equ EEAR6 = 6 ; EEPROM Read/Write Access Bit 6 .equ EEAR7 = 7 ; EEPROM Read/Write Access Bit 7 ; EEDR - EEPROM Data Register .equ EEDR0 = 0 ; EEPROM Data Register bit 0 .equ EEDR1 = 1 ; EEPROM Data Register bit 1 .equ EEDR2 = 2 ; EEPROM Data Register bit 2 .equ EEDR3 = 3 ; EEPROM Data Register bit 3 .equ EEDR4 = 4 ; EEPROM Data Register bit 4 .equ EEDR5 = 5 ; EEPROM Data Register bit 5 .equ EEDR6 = 6 ; EEPROM Data Register bit 6 .equ EEDR7 = 7 ; EEPROM Data Register bit 7 ; EECR - EEPROM Control Register .equ EERE = 0 ; EEPROM Read Enable .equ EEPE = 1 ; EEPROM Write Enable .equ EEWE = EEPE ; For compatibility .equ EEMPE = 2 ; EEPROM Master Write Enable .equ EEMWE = EEMPE ; For compatibility .equ EERIE = 3 ; EEPROM Ready Interrupt Enable .equ EEPM0 = 4 ; EEPROM Programming Mode Bit 0 .equ EEPM1 = 5 ; EEPROM Programming Mode Bit 1 ; ***** LOCKSBITS ******************************************************** .equ LB1 = 0 ; Lockbit .equ LB2 = 1 ; Lockbit ; ***** FUSES ************************************************************ ; LOW fuse bits .equ CKSEL0 = 0 ; Select Clock Source .equ CKSEL1 = 1 ; Select Clock Source .equ CKSEL2 = 2 ; Select Clock Source .equ CKSEL3 = 3 ; Select Clock Source .equ SUT0 = 4 ; Select start-up time .equ SUT1 = 5 ; Select start-up time .equ CKOUT = 6 ; Clock output .equ CKDIV8 = 7 ; Divide clock by 8 ; HIGH fuse bits .equ BODLEVEL0 = 0 ; Brown-out Detector trigger level .equ BODLEVEL1 = 1 ; Brown-out Detector trigger level .equ BODLEVEL2 = 2 ; Brown-out Detector trigger level .equ EESAVE = 3 ; EEPROM memory is preserved through chip erase .equ WDTON = 4 ; Watchdog Timer Always On .equ SPIEN = 5 ; Enable Serial programming and Data Downloading .equ DWEN = 6 ; debugWIRE Enable .equ RSTDISBL = 7 ; External reset disable ; EXTENDED fuse bits ;.equ SELFPRGEN = 0 ; Self Programming Enable ; ***** CPU REGISTER DEFINITIONS ***************************************** .def XH = r27 .def XL = r26 .def YH = r29 .def YL = r28 .def ZH = r31 .def ZL = r30 ; ***** DATA MEMORY DECLARATIONS ***************************************** .equ FLASHEND = 0x07ff ; Note: Word address .equ IOEND = 0x00ff .equ SRAM_START = 0x0100 .equ SRAM_SIZE = 512 .equ RAMEND = 0x02ff .equ XRAMEND = 0x0000 .equ E2END = 0x00ff .equ EEPROMEND = 0x00ff .equ EEADRBITS = 8 #pragma AVRPART MEMORY PROG_FLASH 4096 #pragma AVRPART MEMORY EEPROM 256 #pragma AVRPART MEMORY INT_SRAM SIZE 512 #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 ; ***** BOOTLOADER DECLARATIONS ****************************************** .equ NRWW_START_ADDR = 0x0 .equ NRWW_STOP_ADDR = 0x7ff .equ RWW_START_ADDR = 0x0 .equ RWW_STOP_ADDR = 0x0 .equ PAGESIZE = 32 ; ***** INTERRUPT VECTORS ************************************************ .equ INT0addr = 0x0001 ; External Interrupt Request 0 .equ INT1addr = 0x0002 ; External Interrupt Request 1 .equ PCI0addr = 0x0003 ; Pin Change Interrupt Request 0 .equ PCI1addr = 0x0004 ; Pin Change Interrupt Request 0 .equ PCI2addr = 0x0005 ; Pin Change Interrupt Request 1 .equ WDTaddr = 0x0006 ; Watchdog Time-out Interrupt .equ OC2Aaddr = 0x0007 ; Timer/Counter2 Compare Match A .equ OC2Baddr = 0x0008 ; Timer/Counter2 Compare Match A .equ OVF2addr = 0x0009 ; Timer/Counter2 Overflow .equ ICP1addr = 0x000a ; Timer/Counter1 Capture Event .equ OC1Aaddr = 0x000b ; Timer/Counter1 Compare Match A .equ OC1Baddr = 0x000c ; Timer/Counter1 Compare Match B .equ OVF1addr = 0x000d ; Timer/Counter1 Overflow .equ OC0Aaddr = 0x000e ; TimerCounter0 Compare Match A .equ OC0Baddr = 0x000f ; TimerCounter0 Compare Match B .equ OVF0addr = 0x0010 ; Timer/Couner0 Overflow .equ SPIaddr = 0x0011 ; SPI Serial Transfer Complete .equ URXCaddr = 0x0012 ; USART Rx Complete .equ UDREaddr = 0x0013 ; USART, Data Register Empty .equ UTXCaddr = 0x0014 ; USART Tx Complete .equ ADCCaddr = 0x0015 ; ADC Conversion Complete .equ ERDYaddr = 0x0016 ; EEPROM Ready .equ ACIaddr = 0x0017 ; Analog Comparator .equ TWIaddr = 0x0018 ; Two-wire Serial Interface .equ SPMRaddr = 0x0019 ; Store Program Memory Read .equ INT_VECTORS_SIZE = 26 ; size in words #endif /* _M48DEF_INC_ */ ; ***** END OF FILE ****************************************************** /* Copyright (c) 2004, Theodore A. Roth All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom48.h,v 1.3.2.4 2009/02/11 18:05:29 arcanum Exp $ */ #ifndef _AVR_IOM48_H_ #define _AVR_IOM48_H_ 1 #include <avr/iomx8.h> /* Constants */ #define SPM_PAGESIZE 64 #define RAMEND 0x2FF #define XRAMEND RAMEND #define E2END 0xFF #define E2PAGESIZE 4 #define FLASHEND 0xFFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self Programming Enable */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x92 #define SIGNATURE_2 0x05 #endif /* _AVR_IOM48_H_ */

[m48def.inc]	[iom48.h]
;*** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT **************** ;* Created: 2009-11-03 14:40 *** Source: ATmega48.xml ******** ;*********************************************************************** ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y ;* ;* Number : AVR000 ;* File Name : "m48def.inc" ;* Title : Register/Bit Definitions for the ATmega48 ;* Date : 2009-11-03 ;* Version : 2.35 ;* Support E-mail : avr@atmel.com ;* Target MCU : ATmega48 ;* ;* DESCRIPTION ;* When including this file in the assembly program file, all I/O register ;* names and I/O register bit names appearing in the data book can be used. ;* In addition, the six registers forming the three data pointers X, Y and ;* Z have been assigned names XL - ZH. Highest RAM address for Internal ;* SRAM is also defined ;* ;* The Register names are represented by their hexadecimal address. ;* ;* The Register Bit names are represented by their bit number (0-7). ;* ;* Please observe the difference in using the bit names with instructions ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" ;* (skip if bit in register set/cleared). The following example illustrates ;* this: ;* ;* in r16,PORTB ;read PORTB latch ;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) ;* out PORTB,r16 ;output to PORTB ;* ;* in r16,TIFR ;read the Timer Interrupt Flag Register ;* sbrc r16,TOV0 ;test the overflow flag (use bit#) ;* rjmp TOV0_is_set ;jump if set ;* ... ;otherwise do something else ;*********************************************************************** #ifndef _M48DEF_INC_ #define _M48DEF_INC_ #pragma partinc 0 ; * SPECIFY DEVICE *********************************************** .device ATmega48 #pragma AVRPART ADMIN PART_NAME ATmega48 .equ SIGNATURE_000 = 0x1e .equ SIGNATURE_001 = 0x92 .equ SIGNATURE_002 = 0x05 #pragma AVRPART CORE CORE_VERSION V2E ; * I/O REGISTER DEFINITIONS ************************************* ; NOTE: ; Definitions marked "MEMORY MAPPED"are extended I/O ports ; and cannot be used with IN/OUT instructions .equ UDR0 = 0xc6 ; MEMORY MAPPED .equ UBRR0L = 0xc4 ; MEMORY MAPPED .equ UBRR0H = 0xc5 ; MEMORY MAPPED .equ UCSR0C = 0xc2 ; MEMORY MAPPED .equ UCSR0B = 0xc1 ; MEMORY MAPPED .equ UCSR0A = 0xc0 ; MEMORY MAPPED .equ TWAMR = 0xbd ; MEMORY MAPPED .equ TWCR = 0xbc ; MEMORY MAPPED .equ TWDR = 0xbb ; MEMORY MAPPED .equ TWAR = 0xba ; MEMORY MAPPED .equ TWSR = 0xb9 ; MEMORY MAPPED .equ TWBR = 0xb8 ; MEMORY MAPPED .equ ASSR = 0xb6 ; MEMORY MAPPED .equ OCR2B = 0xb4 ; MEMORY MAPPED .equ OCR2A = 0xb3 ; MEMORY MAPPED .equ TCNT2 = 0xb2 ; MEMORY MAPPED .equ TCCR2B = 0xb1 ; MEMORY MAPPED .equ TCCR2A = 0xb0 ; MEMORY MAPPED .equ OCR1BL = 0x8a ; MEMORY MAPPED .equ OCR1BH = 0x8b ; MEMORY MAPPED .equ OCR1AL = 0x88 ; MEMORY MAPPED .equ OCR1AH = 0x89 ; MEMORY MAPPED .equ ICR1L = 0x86 ; MEMORY MAPPED .equ ICR1H = 0x87 ; MEMORY MAPPED .equ TCNT1L = 0x84 ; MEMORY MAPPED .equ TCNT1H = 0x85 ; MEMORY MAPPED .equ TCCR1C = 0x82 ; MEMORY MAPPED .equ TCCR1B = 0x81 ; MEMORY MAPPED .equ TCCR1A = 0x80 ; MEMORY MAPPED .equ DIDR1 = 0x7f ; MEMORY MAPPED .equ DIDR0 = 0x7e ; MEMORY MAPPED .equ ADMUX = 0x7c ; MEMORY MAPPED .equ ADCSRB = 0x7b ; MEMORY MAPPED .equ ADCSRA = 0x7a ; MEMORY MAPPED .equ ADCH = 0x79 ; MEMORY MAPPED .equ ADCL = 0x78 ; MEMORY MAPPED .equ TIMSK2 = 0x70 ; MEMORY MAPPED .equ TIMSK1 = 0x6f ; MEMORY MAPPED .equ TIMSK0 = 0x6e ; MEMORY MAPPED .equ PCMSK1 = 0x6c ; MEMORY MAPPED .equ PCMSK2 = 0x6d ; MEMORY MAPPED .equ PCMSK0 = 0x6b ; MEMORY MAPPED .equ EICRA = 0x69 ; MEMORY MAPPED .equ PCICR = 0x68 ; MEMORY MAPPED .equ OSCCAL = 0x66 ; MEMORY MAPPED .equ PRR = 0x64 ; MEMORY MAPPED .equ CLKPR = 0x61 ; MEMORY MAPPED .equ WDTCSR = 0x60 ; MEMORY MAPPED .equ SREG = 0x3f .equ SPL = 0x3d .equ SPH = 0x3e .equ SPMCSR = 0x37 .equ MCUCR = 0x35 .equ MCUSR = 0x34 .equ SMCR = 0x33 .equ ACSR = 0x30 .equ SPDR = 0x2e .equ SPSR = 0x2d .equ SPCR = 0x2c .equ GPIOR2 = 0x2b .equ GPIOR1 = 0x2a .equ OCR0B = 0x28 .equ OCR0A = 0x27 .equ TCNT0 = 0x26 .equ TCCR0B = 0x25 .equ TCCR0A = 0x24 .equ GTCCR = 0x23 .equ EEARL = 0x21 .equ EEDR = 0x20 .equ EECR = 0x1f .equ GPIOR0 = 0x1e .equ EIMSK = 0x1d .equ EIFR = 0x1c .equ PCIFR = 0x1b .equ TIFR2 = 0x17 .equ TIFR1 = 0x16 .equ TIFR0 = 0x15 .equ PORTD = 0x0b .equ DDRD = 0x0a .equ PIND = 0x09 .equ PORTC = 0x08 .equ DDRC = 0x07 .equ PINC = 0x06 .equ PORTB = 0x05 .equ DDRB = 0x04 .equ PINB = 0x03 ; * BIT DEFINITIONS ********************************************** ; * USART0 ******************* ; UDR0 - USART I/O Data Register .equ UDR0_0 = 0 ; USART I/O Data Register bit 0 .equ UDR0_1 = 1 ; USART I/O Data Register bit 1 .equ UDR0_2 = 2 ; USART I/O Data Register bit 2 .equ UDR0_3 = 3 ; USART I/O Data Register bit 3 .equ UDR0_4 = 4 ; USART I/O Data Register bit 4 .equ UDR0_5 = 5 ; USART I/O Data Register bit 5 .equ UDR0_6 = 6 ; USART I/O Data Register bit 6 .equ UDR0_7 = 7 ; USART I/O Data Register bit 7 ; UCSR0A - USART Control and Status Register A .equ MPCM0 = 0 ; Multi-processor Communication Mode .equ U2X0 = 1 ; Double the USART transmission speed .equ UPE0 = 2 ; Parity Error .equ DOR0 = 3 ; Data overRun .equ FE0 = 4 ; Framing Error .equ UDRE0 = 5 ; USART Data Register Empty .equ TXC0 = 6 ; USART Transmitt Complete .equ RXC0 = 7 ; USART Receive Complete ; UCSR0B - USART Control and Status Register B .equ TXB80 = 0 ; Transmit Data Bit 8 .equ RXB80 = 1 ; Receive Data Bit 8 .equ UCSZ02 = 2 ; Character Size .equ TXEN0 = 3 ; Transmitter Enable .equ RXEN0 = 4 ; Receiver Enable .equ UDRIE0 = 5 ; USART Data register Empty Interrupt Enable .equ TXCIE0 = 6 ; TX Complete Interrupt Enable .equ RXCIE0 = 7 ; RX Complete Interrupt Enable ; UCSR0C - USART Control and Status Register C .equ UCPOL0 = 0 ; Clock Polarity .equ UCSZ00 = 1 ; Character Size .equ UCPHA0 = UCSZ00 ; For compatibility .equ UCSZ01 = 2 ; Character Size .equ UDORD0 = UCSZ01 ; For compatibility .equ USBS0 = 3 ; Stop Bit Select .equ UPM00 = 4 ; Parity Mode Bit 0 .equ UPM01 = 5 ; Parity Mode Bit 1 .equ UMSEL00 = 6 ; USART Mode Select .equ UMSEL0 = UMSEL00 ; For compatibility .equ UMSEL01 = 7 ; USART Mode Select .equ UMSEL1 = UMSEL01 ; For compatibility ; UBRR0H - USART Baud Rate Register High Byte .equ UBRR8 = 0 ; USART Baud Rate Register bit 8 .equ UBRR9 = 1 ; USART Baud Rate Register bit 9 .equ UBRR10 = 2 ; USART Baud Rate Register bit 10 .equ UBRR11 = 3 ; USART Baud Rate Register bit 11 ; UBRR0L - USART Baud Rate Register Low Byte .equ _UBRR0 = 0 ; USART Baud Rate Register bit 0 .equ _UBRR1 = 1 ; USART Baud Rate Register bit 1 .equ UBRR2 = 2 ; USART Baud Rate Register bit 2 .equ UBRR3 = 3 ; USART Baud Rate Register bit 3 .equ UBRR4 = 4 ; USART Baud Rate Register bit 4 .equ UBRR5 = 5 ; USART Baud Rate Register bit 5 .equ UBRR6 = 6 ; USART Baud Rate Register bit 6 .equ UBRR7 = 7 ; USART Baud Rate Register bit 7 ; * TWI ********************** ; TWAMR - TWI (Slave) Address Mask Register .equ TWAM0 = 1 ; .equ TWAMR0 = TWAM0 ; For compatibility .equ TWAM1 = 2 ; .equ TWAMR1 = TWAM1 ; For compatibility .equ TWAM2 = 3 ; .equ TWAMR2 = TWAM2 ; For compatibility .equ TWAM3 = 4 ; .equ TWAMR3 = TWAM3 ; For compatibility .equ TWAM4 = 5 ; .equ TWAMR4 = TWAM4 ; For compatibility .equ TWAM5 = 6 ; .equ TWAMR5 = TWAM5 ; For compatibility .equ TWAM6 = 7 ; .equ TWAMR6 = TWAM6 ; For compatibility ; TWBR - TWI Bit Rate register .equ TWBR0 = 0 ; .equ TWBR1 = 1 ; .equ TWBR2 = 2 ; .equ TWBR3 = 3 ; .equ TWBR4 = 4 ; .equ TWBR5 = 5 ; .equ TWBR6 = 6 ; .equ TWBR7 = 7 ; ; TWCR - TWI Control Register .equ TWIE = 0 ; TWI Interrupt Enable .equ TWEN = 2 ; TWI Enable Bit .equ TWWC = 3 ; TWI Write Collition Flag .equ TWSTO = 4 ; TWI Stop Condition Bit .equ TWSTA = 5 ; TWI Start Condition Bit .equ TWEA = 6 ; TWI Enable Acknowledge Bit .equ TWINT = 7 ; TWI Interrupt Flag ; TWSR - TWI Status Register .equ TWPS0 = 0 ; TWI Prescaler .equ TWPS1 = 1 ; TWI Prescaler .equ TWS3 = 3 ; TWI Status .equ TWS4 = 4 ; TWI Status .equ TWS5 = 5 ; TWI Status .equ TWS6 = 6 ; TWI Status .equ TWS7 = 7 ; TWI Status ; TWDR - TWI Data register .equ TWD0 = 0 ; TWI Data Register Bit 0 .equ TWD1 = 1 ; TWI Data Register Bit 1 .equ TWD2 = 2 ; TWI Data Register Bit 2 .equ TWD3 = 3 ; TWI Data Register Bit 3 .equ TWD4 = 4 ; TWI Data Register Bit 4 .equ TWD5 = 5 ; TWI Data Register Bit 5 .equ TWD6 = 6 ; TWI Data Register Bit 6 .equ TWD7 = 7 ; TWI Data Register Bit 7 ; TWAR - TWI (Slave) Address register .equ TWGCE = 0 ; TWI General Call Recognition Enable Bit .equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 .equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 .equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 .equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 .equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 .equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 .equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 ; * TIMER_COUNTER_1 ********** ; TIMSK1 - Timer/Counter Interrupt Mask Register .equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable .equ OCIE1A = 1 ; Timer/Counter1 Output CompareA Match Interrupt Enable .equ OCIE1B = 2 ; Timer/Counter1 Output CompareB Match Interrupt Enable .equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable ; TIFR1 - Timer/Counter Interrupt Flag register .equ TOV1 = 0 ; Timer/Counter1 Overflow Flag .equ OCF1A = 1 ; Output Compare Flag 1A .equ OCF1B = 2 ; Output Compare Flag 1B .equ ICF1 = 5 ; Input Capture Flag 1 ; TCCR1A - Timer/Counter1 Control Register A .equ WGM10 = 0 ; Waveform Generation Mode .equ WGM11 = 1 ; Waveform Generation Mode .equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 .equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 .equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0 .equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 ; TCCR1B - Timer/Counter1 Control Register B .equ CS10 = 0 ; Prescaler source of Timer/Counter 1 .equ CS11 = 1 ; Prescaler source of Timer/Counter 1 .equ CS12 = 2 ; Prescaler source of Timer/Counter 1 .equ WGM12 = 3 ; Waveform Generation Mode .equ WGM13 = 4 ; Waveform Generation Mode .equ ICES1 = 6 ; Input Capture 1 Edge Select .equ ICNC1 = 7 ; Input Capture 1 Noise Canceler ; TCCR1C - Timer/Counter1 Control Register C .equ FOC1B = 6 ; .equ FOC1A = 7 ; ; GTCCR - General Timer/Counter Control Register .equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 .equ TSM = 7 ; Timer/Counter Synchronization Mode ; * TIMER_COUNTER_2 ********** ; TIMSK2 - Timer/Counter Interrupt Mask register .equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable .equ TOIE2A = TOIE2 ; For compatibility .equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match A Interrupt Enable .equ OCIE2B = 2 ; Timer/Counter2 Output Compare Match B Interrupt Enable ; TIFR2 - Timer/Counter Interrupt Flag Register .equ TOV2 = 0 ; Timer/Counter2 Overflow Flag .equ OCF2A = 1 ; Output Compare Flag 2A .equ OCF2B = 2 ; Output Compare Flag 2B ; TCCR2A - Timer/Counter2 Control Register A .equ WGM20 = 0 ; Waveform Genration Mode .equ WGM21 = 1 ; Waveform Genration Mode .equ COM2B0 = 4 ; Compare Output Mode bit 0 .equ COM2B1 = 5 ; Compare Output Mode bit 1 .equ COM2A0 = 6 ; Compare Output Mode bit 1 .equ COM2A1 = 7 ; Compare Output Mode bit 1 ; TCCR2B - Timer/Counter2 Control Register B .equ CS20 = 0 ; Clock Select bit 0 .equ CS21 = 1 ; Clock Select bit 1 .equ CS22 = 2 ; Clock Select bit 2 .equ WGM22 = 3 ; Waveform Generation Mode .equ FOC2B = 6 ; Force Output Compare B .equ FOC2A = 7 ; Force Output Compare A ; TCNT2 - Timer/Counter2 .equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 .equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 .equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 .equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 .equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 .equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 .equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 .equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 ; OCR2A - Timer/Counter2 Output Compare Register A .equ OCR2A_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 .equ OCR2A_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 .equ OCR2A_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 .equ OCR2A_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 .equ OCR2A_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 .equ OCR2A_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 .equ OCR2A_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 .equ OCR2A_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 ; OCR2B - Timer/Counter2 Output Compare Register B .equ OCR2B_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 .equ OCR2B_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 .equ OCR2B_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 .equ OCR2B_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 .equ OCR2B_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 .equ OCR2B_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 .equ OCR2B_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 .equ OCR2B_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 ; ASSR - Asynchronous Status Register .equ TCR2BUB = 0 ; Timer/Counter Control Register2 Update Busy .equ TCR2AUB = 1 ; Timer/Counter Control Register2 Update Busy .equ OCR2BUB = 2 ; Output Compare Register 2 Update Busy .equ OCR2AUB = 3 ; Output Compare Register2 Update Busy .equ TCN2UB = 4 ; Timer/Counter2 Update Busy .equ AS2 = 5 ; Asynchronous Timer/Counter2 .equ EXCLK = 6 ; Enable External Clock Input ; GTCCR - General Timer Counter Control register .equ PSRASY = 1 ; Prescaler Reset Timer/Counter2 .equ PSR2 = PSRASY ; For compatibility ;.equ TSM = 7 ; Timer/Counter Synchronization Mode ; * AD_CONVERTER ************* ; ADMUX - The ADC multiplexer Selection Register .equ MUX0 = 0 ; Analog Channel and Gain Selection Bits .equ MUX1 = 1 ; Analog Channel and Gain Selection Bits .equ MUX2 = 2 ; Analog Channel and Gain Selection Bits .equ MUX3 = 3 ; Analog Channel and Gain Selection Bits .equ ADLAR = 5 ; Left Adjust Result .equ REFS0 = 6 ; Reference Selection Bit 0 .equ REFS1 = 7 ; Reference Selection Bit 1 ; ADCSRA - The ADC Control and Status register A .equ ADPS0 = 0 ; ADC Prescaler Select Bits .equ ADPS1 = 1 ; ADC Prescaler Select Bits .equ ADPS2 = 2 ; ADC Prescaler Select Bits .equ ADIE = 3 ; ADC Interrupt Enable .equ ADIF = 4 ; ADC Interrupt Flag .equ ADATE = 5 ; ADC Auto Trigger Enable .equ ADSC = 6 ; ADC Start Conversion .equ ADEN = 7 ; ADC Enable ; ADCSRB - The ADC Control and Status register B .equ ADTS0 = 0 ; ADC Auto Trigger Source bit 0 .equ ADTS1 = 1 ; ADC Auto Trigger Source bit 1 .equ ADTS2 = 2 ; ADC Auto Trigger Source bit 2 .equ ACME = 6 ; ; ADCH - ADC Data Register High Byte .equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 .equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 .equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 .equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 .equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 .equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 .equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 .equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 ; ADCL - ADC Data Register Low Byte .equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 .equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 .equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 .equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 .equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 .equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 .equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 .equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 ; DIDR0 - Digital Input Disable Register .equ ADC0D = 0 ; .equ ADC1D = 1 ; .equ ADC2D = 2 ; .equ ADC3D = 3 ; .equ ADC4D = 4 ; .equ ADC5D = 5 ; ; * ANALOG_COMPARATOR ******** ; ACSR - Analog Comparator Control And Status Register .equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 .equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 .equ ACIC = 2 ; Analog Comparator Input Capture Enable .equ ACIE = 3 ; Analog Comparator Interrupt Enable .equ ACI = 4 ; Analog Comparator Interrupt Flag .equ ACO = 5 ; Analog Compare Output .equ ACBG = 6 ; Analog Comparator Bandgap Select .equ ACD = 7 ; Analog Comparator Disable ; DIDR1 - Digital Input Disable Register 1 .equ AIN0D = 0 ; AIN0 Digital Input Disable .equ AIN1D = 1 ; AIN1 Digital Input Disable ; * PORTB ******************** ; PORTB - Port B Data Register .equ PORTB0 = 0 ; Port B Data Register bit 0 .equ PB0 = 0 ; For compatibility .equ PORTB1 = 1 ; Port B Data Register bit 1 .equ PB1 = 1 ; For compatibility .equ PORTB2 = 2 ; Port B Data Register bit 2 .equ PB2 = 2 ; For compatibility .equ PORTB3 = 3 ; Port B Data Register bit 3 .equ PB3 = 3 ; For compatibility .equ PORTB4 = 4 ; Port B Data Register bit 4 .equ PB4 = 4 ; For compatibility .equ PORTB5 = 5 ; Port B Data Register bit 5 .equ PB5 = 5 ; For compatibility .equ PORTB6 = 6 ; Port B Data Register bit 6 .equ PB6 = 6 ; For compatibility .equ PORTB7 = 7 ; Port B Data Register bit 7 .equ PB7 = 7 ; For compatibility ; DDRB - Port B Data Direction Register .equ DDB0 = 0 ; Port B Data Direction Register bit 0 .equ DDB1 = 1 ; Port B Data Direction Register bit 1 .equ DDB2 = 2 ; Port B Data Direction Register bit 2 .equ DDB3 = 3 ; Port B Data Direction Register bit 3 .equ DDB4 = 4 ; Port B Data Direction Register bit 4 .equ DDB5 = 5 ; Port B Data Direction Register bit 5 .equ DDB6 = 6 ; Port B Data Direction Register bit 6 .equ DDB7 = 7 ; Port B Data Direction Register bit 7 ; PINB - Port B Input Pins .equ PINB0 = 0 ; Port B Input Pins bit 0 .equ PINB1 = 1 ; Port B Input Pins bit 1 .equ PINB2 = 2 ; Port B Input Pins bit 2 .equ PINB3 = 3 ; Port B Input Pins bit 3 .equ PINB4 = 4 ; Port B Input Pins bit 4 .equ PINB5 = 5 ; Port B Input Pins bit 5 .equ PINB6 = 6 ; Port B Input Pins bit 6 .equ PINB7 = 7 ; Port B Input Pins bit 7 ; * PORTC ******************** ; PORTC - Port C Data Register .equ PORTC0 = 0 ; Port C Data Register bit 0 .equ PC0 = 0 ; For compatibility .equ PORTC1 = 1 ; Port C Data Register bit 1 .equ PC1 = 1 ; For compatibility .equ PORTC2 = 2 ; Port C Data Register bit 2 .equ PC2 = 2 ; For compatibility .equ PORTC3 = 3 ; Port C Data Register bit 3 .equ PC3 = 3 ; For compatibility .equ PORTC4 = 4 ; Port C Data Register bit 4 .equ PC4 = 4 ; For compatibility .equ PORTC5 = 5 ; Port C Data Register bit 5 .equ PC5 = 5 ; For compatibility .equ PORTC6 = 6 ; Port C Data Register bit 6 .equ PC6 = 6 ; For compatibility ; DDRC - Port C Data Direction Register .equ DDC0 = 0 ; Port C Data Direction Register bit 0 .equ DDC1 = 1 ; Port C Data Direction Register bit 1 .equ DDC2 = 2 ; Port C Data Direction Register bit 2 .equ DDC3 = 3 ; Port C Data Direction Register bit 3 .equ DDC4 = 4 ; Port C Data Direction Register bit 4 .equ DDC5 = 5 ; Port C Data Direction Register bit 5 .equ DDC6 = 6 ; Port C Data Direction Register bit 6 ; PINC - Port C Input Pins .equ PINC0 = 0 ; Port C Input Pins bit 0 .equ PINC1 = 1 ; Port C Input Pins bit 1 .equ PINC2 = 2 ; Port C Input Pins bit 2 .equ PINC3 = 3 ; Port C Input Pins bit 3 .equ PINC4 = 4 ; Port C Input Pins bit 4 .equ PINC5 = 5 ; Port C Input Pins bit 5 .equ PINC6 = 6 ; Port C Input Pins bit 6 ; * PORTD ******************** ; PORTD - Port D Data Register .equ PORTD0 = 0 ; Port D Data Register bit 0 .equ PD0 = 0 ; For compatibility .equ PORTD1 = 1 ; Port D Data Register bit 1 .equ PD1 = 1 ; For compatibility .equ PORTD2 = 2 ; Port D Data Register bit 2 .equ PD2 = 2 ; For compatibility .equ PORTD3 = 3 ; Port D Data Register bit 3 .equ PD3 = 3 ; For compatibility .equ PORTD4 = 4 ; Port D Data Register bit 4 .equ PD4 = 4 ; For compatibility .equ PORTD5 = 5 ; Port D Data Register bit 5 .equ PD5 = 5 ; For compatibility .equ PORTD6 = 6 ; Port D Data Register bit 6 .equ PD6 = 6 ; For compatibility .equ PORTD7 = 7 ; Port D Data Register bit 7 .equ PD7 = 7 ; For compatibility ; DDRD - Port D Data Direction Register .equ DDD0 = 0 ; Port D Data Direction Register bit 0 .equ DDD1 = 1 ; Port D Data Direction Register bit 1 .equ DDD2 = 2 ; Port D Data Direction Register bit 2 .equ DDD3 = 3 ; Port D Data Direction Register bit 3 .equ DDD4 = 4 ; Port D Data Direction Register bit 4 .equ DDD5 = 5 ; Port D Data Direction Register bit 5 .equ DDD6 = 6 ; Port D Data Direction Register bit 6 .equ DDD7 = 7 ; Port D Data Direction Register bit 7 ; PIND - Port D Input Pins .equ PIND0 = 0 ; Port D Input Pins bit 0 .equ PIND1 = 1 ; Port D Input Pins bit 1 .equ PIND2 = 2 ; Port D Input Pins bit 2 .equ PIND3 = 3 ; Port D Input Pins bit 3 .equ PIND4 = 4 ; Port D Input Pins bit 4 .equ PIND5 = 5 ; Port D Input Pins bit 5 .equ PIND6 = 6 ; Port D Input Pins bit 6 .equ PIND7 = 7 ; Port D Input Pins bit 7 ; * TIMER_COUNTER_0 ********** ; TIMSK0 - Timer/Counter0 Interrupt Mask Register .equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable .equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable .equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable ; TIFR0 - Timer/Counter0 Interrupt Flag register .equ TOV0 = 0 ; Timer/Counter0 Overflow Flag .equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0A .equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B ; TCCR0A - Timer/Counter Control Register A .equ WGM00 = 0 ; Waveform Generation Mode .equ WGM01 = 1 ; Waveform Generation Mode .equ COM0B0 = 4 ; Compare Output Mode, Fast PWm .equ COM0B1 = 5 ; Compare Output Mode, Fast PWm .equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode .equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode ; TCCR0B - Timer/Counter Control Register B .equ CS00 = 0 ; Clock Select .equ CS01 = 1 ; Clock Select .equ CS02 = 2 ; Clock Select .equ WGM02 = 3 ; .equ FOC0B = 6 ; Force Output Compare B .equ FOC0A = 7 ; Force Output Compare A ; TCNT0 - Timer/Counter0 .equ TCNT0_0 = 0 ; .equ TCNT0_1 = 1 ; .equ TCNT0_2 = 2 ; .equ TCNT0_3 = 3 ; .equ TCNT0_4 = 4 ; .equ TCNT0_5 = 5 ; .equ TCNT0_6 = 6 ; .equ TCNT0_7 = 7 ; ; OCR0A - Timer/Counter0 Output Compare Register .equ OCR0A_0 = 0 ; .equ OCR0A_1 = 1 ; .equ OCR0A_2 = 2 ; .equ OCR0A_3 = 3 ; .equ OCR0A_4 = 4 ; .equ OCR0A_5 = 5 ; .equ OCR0A_6 = 6 ; .equ OCR0A_7 = 7 ; ; OCR0B - Timer/Counter0 Output Compare Register .equ OCR0B_0 = 0 ; .equ OCR0B_1 = 1 ; .equ OCR0B_2 = 2 ; .equ OCR0B_3 = 3 ; .equ OCR0B_4 = 4 ; .equ OCR0B_5 = 5 ; .equ OCR0B_6 = 6 ; .equ OCR0B_7 = 7 ; ; GTCCR - General Timer/Counter Control Register ;.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 .equ PSR10 = PSRSYNC ; For compatibility ;.equ TSM = 7 ; Timer/Counter Synchronization Mode ; * EXTERNAL_INTERRUPT ******* ; EICRA - External Interrupt Control Register .equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0 .equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1 .equ ISC10 = 2 ; External Interrupt Sense Control 1 Bit 0 .equ ISC11 = 3 ; External Interrupt Sense Control 1 Bit 1 ; EIMSK - External Interrupt Mask Register .equ INT0 = 0 ; External Interrupt Request 0 Enable .equ INT1 = 1 ; External Interrupt Request 1 Enable ; EIFR - External Interrupt Flag Register .equ INTF0 = 0 ; External Interrupt Flag 0 .equ INTF1 = 1 ; External Interrupt Flag 1 ; PCICR - Pin Change Interrupt Control Register .equ PCIE0 = 0 ; Pin Change Interrupt Enable 0 .equ PCIE1 = 1 ; Pin Change Interrupt Enable 1 .equ PCIE2 = 2 ; Pin Change Interrupt Enable 2 ; PCMSK2 - Pin Change Mask Register 2 .equ PCINT16 = 0 ; Pin Change Enable Mask 16 .equ PCINT17 = 1 ; Pin Change Enable Mask 17 .equ PCINT18 = 2 ; Pin Change Enable Mask 18 .equ PCINT19 = 3 ; Pin Change Enable Mask 19 .equ PCINT20 = 4 ; Pin Change Enable Mask 20 .equ PCINT21 = 5 ; Pin Change Enable Mask 21 .equ PCINT22 = 6 ; Pin Change Enable Mask 22 .equ PCINT23 = 7 ; Pin Change Enable Mask 23 ; PCMSK1 - Pin Change Mask Register 1 .equ PCINT8 = 0 ; Pin Change Enable Mask 8 .equ PCINT9 = 1 ; Pin Change Enable Mask 9 .equ PCINT10 = 2 ; Pin Change Enable Mask 10 .equ PCINT11 = 3 ; Pin Change Enable Mask 11 .equ PCINT12 = 4 ; Pin Change Enable Mask 12 .equ PCINT13 = 5 ; Pin Change Enable Mask 13 .equ PCINT14 = 6 ; Pin Change Enable Mask 14 ; PCMSK0 - Pin Change Mask Register 0 .equ PCINT0 = 0 ; Pin Change Enable Mask 0 .equ PCINT1 = 1 ; Pin Change Enable Mask 1 .equ PCINT2 = 2 ; Pin Change Enable Mask 2 .equ PCINT3 = 3 ; Pin Change Enable Mask 3 .equ PCINT4 = 4 ; Pin Change Enable Mask 4 .equ PCINT5 = 5 ; Pin Change Enable Mask 5 .equ PCINT6 = 6 ; Pin Change Enable Mask 6 .equ PCINT7 = 7 ; Pin Change Enable Mask 7 ; PCIFR - Pin Change Interrupt Flag Register .equ PCIF0 = 0 ; Pin Change Interrupt Flag 0 .equ PCIF1 = 1 ; Pin Change Interrupt Flag 1 .equ PCIF2 = 2 ; Pin Change Interrupt Flag 2 ; * SPI ********************** ; SPDR - SPI Data Register .equ SPDR0 = 0 ; SPI Data Register bit 0 .equ SPDR1 = 1 ; SPI Data Register bit 1 .equ SPDR2 = 2 ; SPI Data Register bit 2 .equ SPDR3 = 3 ; SPI Data Register bit 3 .equ SPDR4 = 4 ; SPI Data Register bit 4 .equ SPDR5 = 5 ; SPI Data Register bit 5 .equ SPDR6 = 6 ; SPI Data Register bit 6 .equ SPDR7 = 7 ; SPI Data Register bit 7 ; SPSR - SPI Status Register .equ SPI2X = 0 ; Double SPI Speed Bit .equ WCOL = 6 ; Write Collision Flag .equ SPIF = 7 ; SPI Interrupt Flag ; SPCR - SPI Control Register .equ SPR0 = 0 ; SPI Clock Rate Select 0 .equ SPR1 = 1 ; SPI Clock Rate Select 1 .equ CPHA = 2 ; Clock Phase .equ CPOL = 3 ; Clock polarity .equ MSTR = 4 ; Master/Slave Select .equ DORD = 5 ; Data Order .equ SPE = 6 ; SPI Enable .equ SPIE = 7 ; SPI Interrupt Enable ; * CPU ********************** ; SREG - Status Register .equ SREG_C = 0 ; Carry Flag .equ SREG_Z = 1 ; Zero Flag .equ SREG_N = 2 ; Negative Flag .equ SREG_V = 3 ; Two's Complement Overflow Flag .equ SREG_S = 4 ; Sign Bit .equ SREG_H = 5 ; Half Carry Flag .equ SREG_T = 6 ; Bit Copy Storage .equ SREG_I = 7 ; Global Interrupt Enable ; OSCCAL - Oscillator Calibration Value .equ CAL0 = 0 ; Oscillator Calibration Value Bit0 .equ CAL1 = 1 ; Oscillator Calibration Value Bit1 .equ CAL2 = 2 ; Oscillator Calibration Value Bit2 .equ CAL3 = 3 ; Oscillator Calibration Value Bit3 .equ CAL4 = 4 ; Oscillator Calibration Value Bit4 .equ CAL5 = 5 ; Oscillator Calibration Value Bit5 .equ CAL6 = 6 ; Oscillator Calibration Value Bit6 .equ CAL7 = 7 ; Oscillator Calibration Value Bit7 ; CLKPR - Clock Prescale Register .equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 .equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 .equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 .equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 .equ CLKPCE = 7 ; Clock Prescaler Change Enable ; SPMCSR - Store Program Memory Control Register .equ SELFPRGEN = 0 ; Self Programming Enable .equ PGERS = 1 ; Page Erase .equ PGWRT = 2 ; Page Write .equ BLBSET = 3 ; Boot Lock Bit Set .equ RWWSRE = 4 ; Read-While-Write section read enable .equ RWWSB = 6 ; Read-While-Write Section Busy .equ SPMIE = 7 ; SPM Interrupt Enable ; MCUCR - MCU Control Register .equ PUD = 4 ; ; MCUSR - MCU Status Register .equ PORF = 0 ; Power-on reset flag .equ EXTRF = 1 ; External Reset Flag .equ EXTREF = EXTRF ; For compatibility .equ BORF = 2 ; Brown-out Reset Flag .equ WDRF = 3 ; Watchdog Reset Flag ; SMCR - .equ SE = 0 ; .equ SM0 = 1 ; .equ SM1 = 2 ; .equ SM2 = 3 ; ; GPIOR2 - General Purpose I/O Register 2 .equ GPIOR20 = 0 ; .equ GPIOR21 = 1 ; .equ GPIOR22 = 2 ; .equ GPIOR23 = 3 ; .equ GPIOR24 = 4 ; .equ GPIOR25 = 5 ; .equ GPIOR26 = 6 ; .equ GPIOR27 = 7 ; ; GPIOR1 - General Purpose I/O Register 1 .equ GPIOR10 = 0 ; .equ GPIOR11 = 1 ; .equ GPIOR12 = 2 ; .equ GPIOR13 = 3 ; .equ GPIOR14 = 4 ; .equ GPIOR15 = 5 ; .equ GPIOR16 = 6 ; .equ GPIOR17 = 7 ; ; GPIOR0 - General Purpose I/O Register 0 .equ GPIOR00 = 0 ; .equ GPIOR01 = 1 ; .equ GPIOR02 = 2 ; .equ GPIOR03 = 3 ; .equ GPIOR04 = 4 ; .equ GPIOR05 = 5 ; .equ GPIOR06 = 6 ; .equ GPIOR07 = 7 ; ; PRR - Power Reduction Register .equ PRADC = 0 ; Power Reduction ADC .equ PRUSART0 = 1 ; Power Reduction USART .equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface .equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 .equ PRTIM0 = 5 ; Power Reduction Timer/Counter0 .equ PRTIM2 = 6 ; Power Reduction Timer/Counter2 .equ PRTWI = 7 ; Power Reduction TWI ; * WATCHDOG ***************** ; WDTCSR - Watchdog Timer Control Register .equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 .equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 .equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 .equ WDE = 3 ; Watch Dog Enable .equ WDCE = 4 ; Watchdog Change Enable .equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3 .equ WDIE = 6 ; Watchdog Timeout Interrupt Enable .equ WDIF = 7 ; Watchdog Timeout Interrupt Flag ; * EEPROM ******************* ; EEARL - EEPROM Address Register Low Byte .equ EEAR0 = 0 ; EEPROM Read/Write Access Bit 0 .equ EEAR1 = 1 ; EEPROM Read/Write Access Bit 1 .equ EEAR2 = 2 ; EEPROM Read/Write Access Bit 2 .equ EEAR3 = 3 ; EEPROM Read/Write Access Bit 3 .equ EEAR4 = 4 ; EEPROM Read/Write Access Bit 4 .equ EEAR5 = 5 ; EEPROM Read/Write Access Bit 5 .equ EEAR6 = 6 ; EEPROM Read/Write Access Bit 6 .equ EEAR7 = 7 ; EEPROM Read/Write Access Bit 7 ; EEDR - EEPROM Data Register .equ EEDR0 = 0 ; EEPROM Data Register bit 0 .equ EEDR1 = 1 ; EEPROM Data Register bit 1 .equ EEDR2 = 2 ; EEPROM Data Register bit 2 .equ EEDR3 = 3 ; EEPROM Data Register bit 3 .equ EEDR4 = 4 ; EEPROM Data Register bit 4 .equ EEDR5 = 5 ; EEPROM Data Register bit 5 .equ EEDR6 = 6 ; EEPROM Data Register bit 6 .equ EEDR7 = 7 ; EEPROM Data Register bit 7 ; EECR - EEPROM Control Register .equ EERE = 0 ; EEPROM Read Enable .equ EEPE = 1 ; EEPROM Write Enable .equ EEWE = EEPE ; For compatibility .equ EEMPE = 2 ; EEPROM Master Write Enable .equ EEMWE = EEMPE ; For compatibility .equ EERIE = 3 ; EEPROM Ready Interrupt Enable .equ EEPM0 = 4 ; EEPROM Programming Mode Bit 0 .equ EEPM1 = 5 ; EEPROM Programming Mode Bit 1 ; * LOCKSBITS **************************************************** .equ LB1 = 0 ; Lockbit .equ LB2 = 1 ; Lockbit ; * FUSES ******************************************************** ; LOW fuse bits .equ CKSEL0 = 0 ; Select Clock Source .equ CKSEL1 = 1 ; Select Clock Source .equ CKSEL2 = 2 ; Select Clock Source .equ CKSEL3 = 3 ; Select Clock Source .equ SUT0 = 4 ; Select start-up time .equ SUT1 = 5 ; Select start-up time .equ CKOUT = 6 ; Clock output .equ CKDIV8 = 7 ; Divide clock by 8 ; HIGH fuse bits .equ BODLEVEL0 = 0 ; Brown-out Detector trigger level .equ BODLEVEL1 = 1 ; Brown-out Detector trigger level .equ BODLEVEL2 = 2 ; Brown-out Detector trigger level .equ EESAVE = 3 ; EEPROM memory is preserved through chip erase .equ WDTON = 4 ; Watchdog Timer Always On .equ SPIEN = 5 ; Enable Serial programming and Data Downloading .equ DWEN = 6 ; debugWIRE Enable .equ RSTDISBL = 7 ; External reset disable ; EXTENDED fuse bits ;.equ SELFPRGEN = 0 ; Self Programming Enable ; * CPU REGISTER DEFINITIONS ************************************* .def XH = r27 .def XL = r26 .def YH = r29 .def YL = r28 .def ZH = r31 .def ZL = r30 ; * DATA MEMORY DECLARATIONS ************************************* .equ FLASHEND = 0x07ff ; Note: Word address .equ IOEND = 0x00ff .equ SRAM_START = 0x0100 .equ SRAM_SIZE = 512 .equ RAMEND = 0x02ff .equ XRAMEND = 0x0000 .equ E2END = 0x00ff .equ EEPROMEND = 0x00ff .equ EEADRBITS = 8 #pragma AVRPART MEMORY PROG_FLASH 4096 #pragma AVRPART MEMORY EEPROM 256 #pragma AVRPART MEMORY INT_SRAM SIZE 512 #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 ; * BOOTLOADER DECLARATIONS ************************************** .equ NRWW_START_ADDR = 0x0 .equ NRWW_STOP_ADDR = 0x7ff .equ RWW_START_ADDR = 0x0 .equ RWW_STOP_ADDR = 0x0 .equ PAGESIZE = 32 ; * INTERRUPT VECTORS ********************************************** .equ INT0addr = 0x0001 ; External Interrupt Request 0 .equ INT1addr = 0x0002 ; External Interrupt Request 1 .equ PCI0addr = 0x0003 ; Pin Change Interrupt Request 0 .equ PCI1addr = 0x0004 ; Pin Change Interrupt Request 0 .equ PCI2addr = 0x0005 ; Pin Change Interrupt Request 1 .equ WDTaddr = 0x0006 ; Watchdog Time-out Interrupt .equ OC2Aaddr = 0x0007 ; Timer/Counter2 Compare Match A .equ OC2Baddr = 0x0008 ; Timer/Counter2 Compare Match A .equ OVF2addr = 0x0009 ; Timer/Counter2 Overflow .equ ICP1addr = 0x000a ; Timer/Counter1 Capture Event .equ OC1Aaddr = 0x000b ; Timer/Counter1 Compare Match A .equ OC1Baddr = 0x000c ; Timer/Counter1 Compare Match B .equ OVF1addr = 0x000d ; Timer/Counter1 Overflow .equ OC0Aaddr = 0x000e ; TimerCounter0 Compare Match A .equ OC0Baddr = 0x000f ; TimerCounter0 Compare Match B .equ OVF0addr = 0x0010 ; Timer/Couner0 Overflow .equ SPIaddr = 0x0011 ; SPI Serial Transfer Complete .equ URXCaddr = 0x0012 ; USART Rx Complete .equ UDREaddr = 0x0013 ; USART, Data Register Empty .equ UTXCaddr = 0x0014 ; USART Tx Complete .equ ADCCaddr = 0x0015 ; ADC Conversion Complete .equ ERDYaddr = 0x0016 ; EEPROM Ready .equ ACIaddr = 0x0017 ; Analog Comparator .equ TWIaddr = 0x0018 ; Two-wire Serial Interface .equ SPMRaddr = 0x0019 ; Store Program Memory Read .equ INT_VECTORS_SIZE = 26 ; size in words #endif /* _M48DEF_INC_ / ; ** END OF FILE ****************************************************	/* Copyright (c) 2004, Theodore A. Roth All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. / / $Id: iom48.h,v 1.3.2.4 2009/02/11 18:05:29 arcanum Exp $ / #ifndef _AVR_IOM48_H_ #define _AVR_IOM48_H_ 1 #include <avr/iomx8.h> / Constants / #define SPM_PAGESIZE 64 #define RAMEND 0x2FF #define XRAMEND RAMEND #define E2END 0xFF #define E2PAGESIZE 4 #define FLASHEND 0xFFF / Fuses / #define FUSE_MEMORY_SIZE 3 / Low Fuse Byte / #define FUSE_CKSEL0 (unsigned char)~_BV(0) / Select Clock Source / #define FUSE_CKSEL1 (unsigned char)~_BV(1) / Select Clock Source / #define FUSE_CKSEL2 (unsigned char)~_BV(2) / Select Clock Source / #define FUSE_CKSEL3 (unsigned char)~_BV(3) / Select Clock Source / #define FUSE_SUT0 (unsigned char)~_BV(4) / Select start-up time / #define FUSE_SUT1 (unsigned char)~_BV(5) / Select start-up time / #define FUSE_CKOUT (unsigned char)~_BV(6) / Clock output / #define FUSE_CKDIV8 (unsigned char)~_BV(7) / Divide clock by 8 / #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) / High Fuse Byte / #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) / Brown-out Detector trigger level / #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) / Brown-out Detector trigger level / #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) / Brown-out Detector trigger level / #define FUSE_EESAVE (unsigned char)~_BV(3) / EEPROM memory is preserved through chip erase / #define FUSE_WDTON (unsigned char)~_BV(4) / Watchdog Timer Always On / #define FUSE_SPIEN (unsigned char)~_BV(5) / Enable Serial programming and Data Downloading / #define FUSE_DWEN (unsigned char)~_BV(6) / debugWIRE Enable / #define FUSE_RSTDISBL (unsigned char)~_BV(7) / External reset disable / #define HFUSE_DEFAULT (FUSE_SPIEN) / Extended Fuse Byte / #define FUSE_SELFPRGEN (unsigned char)~_BV(0) / Self Programming Enable / #define EFUSE_DEFAULT (0xFF) / Lock Bits / #define __LOCK_BITS_EXIST / Signature / #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x92 #define SIGNATURE_2 0x05 #endif / _AVR_IOM48_H_ */

ATmega64

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[m64def.inc] [iom64.h]

;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** ;***** Created: 2009-11-03 14:40 ******* Source: ATmega64.xml ************ ;************************************************************************* ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y ;* ;* Number : AVR000 ;* File Name : "m64def.inc" ;* Title : Register/Bit Definitions for the ATmega64 ;* Date : 2009-11-03 ;* Version : 2.35 ;* Support E-mail : avr@atmel.com ;* Target MCU : ATmega64 ;* ;* DESCRIPTION ;* When including this file in the assembly program file, all I/O register ;* names and I/O register bit names appearing in the data book can be used. ;* In addition, the six registers forming the three data pointers X, Y and ;* Z have been assigned names XL - ZH. Highest RAM address for Internal ;* SRAM is also defined ;* ;* The Register names are represented by their hexadecimal address. ;* ;* The Register Bit names are represented by their bit number (0-7). ;* ;* Please observe the difference in using the bit names with instructions ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" ;* (skip if bit in register set/cleared). The following example illustrates ;* this: ;* ;* in r16,PORTB ;read PORTB latch ;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) ;* out PORTB,r16 ;output to PORTB ;* ;* in r16,TIFR ;read the Timer Interrupt Flag Register ;* sbrc r16,TOV0 ;test the overflow flag (use bit#) ;* rjmp TOV0_is_set ;jump if set ;* ... ;otherwise do something else ;************************************************************************* #ifndef _M64DEF_INC_ #define _M64DEF_INC_ #pragma partinc 0 ; ***** SPECIFY DEVICE *************************************************** .device ATmega64 #pragma AVRPART ADMIN PART_NAME ATmega64 .equ SIGNATURE_000 = 0x1e .equ SIGNATURE_001 = 0x96 .equ SIGNATURE_002 = 0x02 #pragma AVRPART CORE CORE_VERSION V2E ; ***** I/O REGISTER DEFINITIONS ***************************************** ; NOTE: ; Definitions marked "MEMORY MAPPED"are extended I/O ports ; and cannot be used with IN/OUT instructions .equ UCSR1C = 0x9d ; MEMORY MAPPED .equ UDR1 = 0x9c ; MEMORY MAPPED .equ UCSR1A = 0x9b ; MEMORY MAPPED .equ UCSR1B = 0x9a ; MEMORY MAPPED .equ UBRR1H = 0x98 ; MEMORY MAPPED .equ UBRR1L = 0x99 ; MEMORY MAPPED .equ UCSR0C = 0x95 ; MEMORY MAPPED .equ UBRR0H = 0x90 ; MEMORY MAPPED .equ ADCSRB = 0x8e ; MEMORY MAPPED .equ TCCR3C = 0x8c ; MEMORY MAPPED .equ TCCR3A = 0x8b ; MEMORY MAPPED .equ TCCR3B = 0x8a ; MEMORY MAPPED .equ TCNT3L = 0x88 ; MEMORY MAPPED .equ TCNT3H = 0x89 ; MEMORY MAPPED .equ OCR3AL = 0x86 ; MEMORY MAPPED .equ OCR3AH = 0x87 ; MEMORY MAPPED .equ OCR3BL = 0x84 ; MEMORY MAPPED .equ OCR3BH = 0x85 ; MEMORY MAPPED .equ OCR3CL = 0x82 ; MEMORY MAPPED .equ OCR3CH = 0x83 ; MEMORY MAPPED .equ ICR3L = 0x80 ; MEMORY MAPPED .equ ICR3H = 0x81 ; MEMORY MAPPED .equ ETIMSK = 0x7d ; MEMORY MAPPED .equ ETIFR = 0x7c ; MEMORY MAPPED .equ TCCR1C = 0x7a ; MEMORY MAPPED .equ OCR1CL = 0x78 ; MEMORY MAPPED .equ OCR1CH = 0x79 ; MEMORY MAPPED .equ TWCR = 0x74 ; MEMORY MAPPED .equ TWDR = 0x73 ; MEMORY MAPPED .equ TWAR = 0x72 ; MEMORY MAPPED .equ TWSR = 0x71 ; MEMORY MAPPED .equ TWBR = 0x70 ; MEMORY MAPPED .equ OSCCAL = 0x6f ; MEMORY MAPPED .equ XMCRA = 0x6d ; MEMORY MAPPED .equ XMCRB = 0x6c ; MEMORY MAPPED .equ EICRA = 0x6a ; MEMORY MAPPED .equ SPMCSR = 0x68 ; MEMORY MAPPED .equ PORTG = 0x65 ; MEMORY MAPPED .equ DDRG = 0x64 ; MEMORY MAPPED .equ PING = 0x63 ; MEMORY MAPPED .equ PORTF = 0x62 ; MEMORY MAPPED .equ DDRF = 0x61 ; MEMORY MAPPED .equ SREG = 0x3f .equ SPL = 0x3d .equ SPH = 0x3e .equ XDIV = 0x3c .equ EICRB = 0x3a .equ EIMSK = 0x39 .equ EIFR = 0x38 .equ TIMSK = 0x37 .equ TIFR = 0x36 .equ MCUCR = 0x35 .equ MCUCSR = 0x34 .equ TCCR0 = 0x33 .equ TCNT0 = 0x32 .equ OCR0 = 0x31 .equ ASSR = 0x30 .equ TCCR1A = 0x2f .equ TCCR1B = 0x2e .equ TCNT1L = 0x2c .equ TCNT1H = 0x2d .equ OCR1AL = 0x2a .equ OCR1AH = 0x2b .equ OCR1BL = 0x28 .equ OCR1BH = 0x29 .equ ICR1L = 0x26 .equ ICR1H = 0x27 .equ TCCR2 = 0x25 .equ TCNT2 = 0x24 .equ OCR2 = 0x23 .equ OCDR = 0x22 .equ WDTCR = 0x21 .equ SFIOR = 0x20 .equ EEARL = 0x1e .equ EEARH = 0x1f .equ EEDR = 0x1d .equ EECR = 0x1c .equ PORTA = 0x1b .equ DDRA = 0x1a .equ PINA = 0x19 .equ PORTB = 0x18 .equ DDRB = 0x17 .equ PINB = 0x16 .equ PORTC = 0x15 .equ DDRC = 0x14 .equ PINC = 0x13 .equ PORTD = 0x12 .equ DDRD = 0x11 .equ PIND = 0x10 .equ SPDR = 0x0f .equ SPSR = 0x0e .equ SPCR = 0x0d .equ UDR0 = 0x0c .equ UCSR0A = 0x0b .equ UCSR0B = 0x0a .equ UBRR0L = 0x09 .equ ACSR = 0x08 .equ ADMUX = 0x07 .equ ADCSRA = 0x06 .equ ADCH = 0x05 .equ ADCL = 0x04 .equ PORTE = 0x03 .equ DDRE = 0x02 .equ PINE = 0x01 .equ PINF = 0x00 ; ***** BIT DEFINITIONS ************************************************** ; ***** ANALOG_COMPARATOR ************ ; SFIOR - Special Function IO Register .equ ACME = 3 ; Analog Comparator Multiplexer Enable ; ACSR - Analog Comparator Control And Status Register .equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 .equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 .equ ACIC = 2 ; Analog Comparator Input Capture Enable .equ ACIE = 3 ; Analog Comparator Interrupt Enable .equ ACI = 4 ; Analog Comparator Interrupt Flag .equ ACO = 5 ; Analog Compare Output .equ ACBG = 6 ; Analog Comparator Bandgap Select .equ ACD = 7 ; Analog Comparator Disable ; ***** AD_CONVERTER ***************** ; ADMUX - The ADC multiplexer Selection Register .equ MUX0 = 0 ; Analog Channel and Gain Selection Bits .equ MUX1 = 1 ; Analog Channel and Gain Selection Bits .equ MUX2 = 2 ; Analog Channel and Gain Selection Bits .equ MUX3 = 3 ; Analog Channel and Gain Selection Bits .equ MUX4 = 4 ; Analog Channel and Gain Selection Bits .equ ADLAR = 5 ; Left Adjust Result .equ REFS0 = 6 ; Reference Selection Bit 0 .equ REFS1 = 7 ; Reference Selection Bit 1 ; ADCSRA - The ADC Control and Status register A .equ ADCSR = ADCSRA ; For compatibility .equ ADPS0 = 0 ; ADC Prescaler Select Bits .equ ADPS1 = 1 ; ADC Prescaler Select Bits .equ ADPS2 = 2 ; ADC Prescaler Select Bits .equ ADIE = 3 ; ADC Interrupt Enable .equ ADIF = 4 ; ADC Interrupt Flag .equ ADATE = 5 ; ADC Auto Trigger Enable .equ ADFR = ADATE ; For compatibility .equ ADSC = 6 ; ADC Start Conversion .equ ADEN = 7 ; ADC Enable ; ADCH - ADC Data Register High Byte .equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 .equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 .equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 .equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 .equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 .equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 .equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 .equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 ; ADCL - ADC Data Register Low Byte .equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 .equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 .equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 .equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 .equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 .equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 .equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 .equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 ; ADCSRB - The ADC Control and Status register B .equ ADTS0 = 0 ; ADC Auto Trigger Source bit 0 .equ ADTS1 = 1 ; ADC Auto Trigger Source bit 1 .equ ADTS2 = 2 ; ADC Auto Trigger Source bit 2 ; ***** SPI ************************** ; SPDR - SPI Data Register .equ SPDR0 = 0 ; SPI Data Register bit 0 .equ SPDR1 = 1 ; SPI Data Register bit 1 .equ SPDR2 = 2 ; SPI Data Register bit 2 .equ SPDR3 = 3 ; SPI Data Register bit 3 .equ SPDR4 = 4 ; SPI Data Register bit 4 .equ SPDR5 = 5 ; SPI Data Register bit 5 .equ SPDR6 = 6 ; SPI Data Register bit 6 .equ SPDR7 = 7 ; SPI Data Register bit 7 ; SPSR - SPI Status Register .equ SPI2X = 0 ; Double SPI Speed Bit .equ WCOL = 6 ; Write Collision Flag .equ SPIF = 7 ; SPI Interrupt Flag ; SPCR - SPI Control Register .equ SPR0 = 0 ; SPI Clock Rate Select 0 .equ SPR1 = 1 ; SPI Clock Rate Select 1 .equ CPHA = 2 ; Clock Phase .equ CPOL = 3 ; Clock polarity .equ MSTR = 4 ; Master/Slave Select .equ DORD = 5 ; Data Order .equ SPE = 6 ; SPI Enable .equ SPIE = 7 ; SPI Interrupt Enable ; ***** TWI ************************** ; TWBR - TWI Bit Rate register .equ I2BR = TWBR ; For compatibility .equ TWBR0 = 0 ; .equ TWBR1 = 1 ; .equ TWBR2 = 2 ; .equ TWBR3 = 3 ; .equ TWBR4 = 4 ; .equ TWBR5 = 5 ; .equ TWBR6 = 6 ; .equ TWBR7 = 7 ; ; TWCR - TWI Control Register .equ I2CR = TWCR ; For compatibility .equ TWIE = 0 ; TWI Interrupt Enable .equ I2IE = TWIE ; For compatibility .equ TWEN = 2 ; TWI Enable Bit .equ I2EN = TWEN ; For compatibility .equ ENI2C = TWEN ; For compatibility .equ TWWC = 3 ; TWI Write Collition Flag .equ I2WC = TWWC ; For compatibility .equ TWSTO = 4 ; TWI Stop Condition Bit .equ I2STO = TWSTO ; For compatibility .equ TWSTA = 5 ; TWI Start Condition Bit .equ I2STA = TWSTA ; For compatibility .equ TWEA = 6 ; TWI Enable Acknowledge Bit .equ I2EA = TWEA ; For compatibility .equ TWINT = 7 ; TWI Interrupt Flag .equ I2INT = TWINT ; For compatibility ; TWSR - TWI Status Register .equ I2SR = TWSR ; For compatibility .equ TWPS0 = 0 ; TWI Prescaler .equ TWS0 = TWPS0 ; For compatibility .equ I2GCE = TWPS0 ; For compatibility .equ TWPS1 = 1 ; TWI Prescaler .equ TWS1 = TWPS1 ; For compatibility .equ TWS3 = 3 ; TWI Status .equ I2S3 = TWS3 ; For compatibility .equ TWS4 = 4 ; TWI Status .equ I2S4 = TWS4 ; For compatibility .equ TWS5 = 5 ; TWI Status .equ I2S5 = TWS5 ; For compatibility .equ TWS6 = 6 ; TWI Status .equ I2S6 = TWS6 ; For compatibility .equ TWS7 = 7 ; TWI Status .equ I2S7 = TWS7 ; For compatibility ; TWDR - TWI Data register .equ I2DR = TWDR ; For compatibility .equ TWD0 = 0 ; TWI Data Register Bit 0 .equ TWD1 = 1 ; TWI Data Register Bit 1 .equ TWD2 = 2 ; TWI Data Register Bit 2 .equ TWD3 = 3 ; TWI Data Register Bit 3 .equ TWD4 = 4 ; TWI Data Register Bit 4 .equ TWD5 = 5 ; TWI Data Register Bit 5 .equ TWD6 = 6 ; TWI Data Register Bit 6 .equ TWD7 = 7 ; TWI Data Register Bit 7 ; TWAR - TWI (Slave) Address register .equ I2AR = TWAR ; For compatibility .equ TWGCE = 0 ; TWI General Call Recognition Enable Bit .equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 .equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 .equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 .equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 .equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 .equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 .equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 ; ***** USART0 *********************** ; UDR0 - USART I/O Data Register .equ UDR00 = 0 ; USART I/O Data Register bit 0 .equ UDR01 = 1 ; USART I/O Data Register bit 1 .equ UDR02 = 2 ; USART I/O Data Register bit 2 .equ UDR03 = 3 ; USART I/O Data Register bit 3 .equ UDR04 = 4 ; USART I/O Data Register bit 4 .equ UDR05 = 5 ; USART I/O Data Register bit 5 .equ UDR06 = 6 ; USART I/O Data Register bit 6 .equ UDR07 = 7 ; USART I/O Data Register bit 7 ; UCSR0A - USART Control and Status Register A .equ MPCM0 = 0 ; Multi-processor Communication Mode .equ U2X0 = 1 ; Double the USART transmission speed .equ UPE0 = 2 ; Parity Error .equ DOR0 = 3 ; Data overRun .equ FE0 = 4 ; Framing Error .equ UDRE0 = 5 ; USART Data Register Empty .equ TXC0 = 6 ; USART Transmitt Complete .equ RXC0 = 7 ; USART Receive Complete ; UCSR0B - USART Control and Status Register B .equ TXB80 = 0 ; Transmit Data Bit 8 .equ RXB80 = 1 ; Receive Data Bit 8 .equ UCSZ02 = 2 ; Character Size .equ UCSZ2 = UCSZ02 ; For compatibility .equ TXEN0 = 3 ; Transmitter Enable .equ RXEN0 = 4 ; Receiver Enable .equ UDRIE0 = 5 ; USART Data register Empty Interrupt Enable .equ TXCIE0 = 6 ; TX Complete Interrupt Enable .equ RXCIE0 = 7 ; RX Complete Interrupt Enable ; UCSR0C - USART Control and Status Register C .equ UCPOL0 = 0 ; Clock Polarity .equ UCSZ00 = 1 ; Character Size .equ UCSZ01 = 2 ; Character Size .equ USBS0 = 3 ; Stop Bit Select .equ UPM00 = 4 ; Parity Mode Bit 0 .equ UPM01 = 5 ; Parity Mode Bit 1 .equ UMSEL0 = 6 ; USART Mode Select ; UBRR0H - USART Baud Rate Register Hight Byte .equ UBRR8 = 0 ; USART Baud Rate Register bit 8 .equ UBRR9 = 1 ; USART Baud Rate Register bit 9 .equ UBRR10 = 2 ; USART Baud Rate Register bit 10 .equ UBRR11 = 3 ; USART Baud Rate Register bit 11 ; UBRR0L - USART Baud Rate Register Low Byte .equ UBRR0 = 0 ; USART Baud Rate Register bit 0 .equ UBRR1 = 1 ; USART Baud Rate Register bit 1 .equ UBRR2 = 2 ; USART Baud Rate Register bit 2 .equ UBRR3 = 3 ; USART Baud Rate Register bit 3 .equ UBRR4 = 4 ; USART Baud Rate Register bit 4 .equ UBRR5 = 5 ; USART Baud Rate Register bit 5 .equ UBRR6 = 6 ; USART Baud Rate Register bit 6 .equ UBRR7 = 7 ; USART Baud Rate Register bit 7 ; ***** USART1 *********************** ; UDR1 - USART I/O Data Register .equ UDR10 = 0 ; USART I/O Data Register bit 0 .equ UDR11 = 1 ; USART I/O Data Register bit 1 .equ UDR12 = 2 ; USART I/O Data Register bit 2 .equ UDR13 = 3 ; USART I/O Data Register bit 3 .equ UDR14 = 4 ; USART I/O Data Register bit 4 .equ UDR15 = 5 ; USART I/O Data Register bit 5 .equ UDR16 = 6 ; USART I/O Data Register bit 6 .equ UDR17 = 7 ; USART I/O Data Register bit 7 ; UCSR1A - USART Control and Status Register A .equ MPCM1 = 0 ; Multi-processor Communication Mode .equ U2X1 = 1 ; Double the USART transmission speed .equ UPE1 = 2 ; Parity Error .equ DOR1 = 3 ; Data overRun .equ FE1 = 4 ; Framing Error .equ UDRE1 = 5 ; USART Data Register Empty .equ TXC1 = 6 ; USART Transmitt Complete .equ RXC1 = 7 ; USART Receive Complete ; UCSR1B - USART Control and Status Register B .equ TXB81 = 0 ; Transmit Data Bit 8 .equ RXB81 = 1 ; Receive Data Bit 8 .equ UCSZ12 = 2 ; Character Size .equ TXEN1 = 3 ; Transmitter Enable .equ RXEN1 = 4 ; Receiver Enable .equ UDRIE1 = 5 ; USART Data register Empty Interrupt Enable .equ TXCIE1 = 6 ; TX Complete Interrupt Enable .equ RXCIE1 = 7 ; RX Complete Interrupt Enable ; UCSR1C - USART Control and Status Register C .equ UCPOL1 = 0 ; Clock Polarity .equ UCSZ10 = 1 ; Character Size .equ UCSZ11 = 2 ; Character Size .equ USBS1 = 3 ; Stop Bit Select .equ UPM10 = 4 ; Parity Mode Bit 0 .equ UPM11 = 5 ; Parity Mode Bit 1 .equ UMSEL1 = 6 ; USART Mode Select ; UBRR1H - USART Baud Rate Register Hight Byte ;.equ UBRR8 = 0 ; USART Baud Rate Register bit 8 ;.equ UBRR9 = 1 ; USART Baud Rate Register bit 9 ;.equ UBRR10 = 2 ; USART Baud Rate Register bit 10 ;.equ UBRR11 = 3 ; USART Baud Rate Register bit 11 ; UBRR1L - USART Baud Rate Register Low Byte ;.equ UBRR0 = 0 ; USART Baud Rate Register bit 0 ;.equ UBRR1 = 1 ; USART Baud Rate Register bit 1 ;.equ UBRR2 = 2 ; USART Baud Rate Register bit 2 ;.equ UBRR3 = 3 ; USART Baud Rate Register bit 3 ;.equ UBRR4 = 4 ; USART Baud Rate Register bit 4 ;.equ UBRR5 = 5 ; USART Baud Rate Register bit 5 ;.equ UBRR6 = 6 ; USART Baud Rate Register bit 6 ;.equ UBRR7 = 7 ; USART Baud Rate Register bit 7 ; ***** CPU ************************** ; SREG - Status Register .equ SREG_C = 0 ; Carry Flag .equ SREG_Z = 1 ; Zero Flag .equ SREG_N = 2 ; Negative Flag .equ SREG_V = 3 ; Two's Complement Overflow Flag .equ SREG_S = 4 ; Sign Bit .equ SREG_H = 5 ; Half Carry Flag .equ SREG_T = 6 ; Bit Copy Storage .equ SREG_I = 7 ; Global Interrupt Enable ; MCUCR - MCU Control Register .equ IVCE = 0 ; Interrupt Vector Change Enable .equ IVSEL = 1 ; Interrupt Vector Select .equ SM2 = 2 ; Sleep Mode Select .equ SM0 = 3 ; Sleep Mode Select .equ SM1 = 4 ; Sleep Mode Select .equ SE = 5 ; Sleep Enable .equ SRW10 = 6 ; External SRAM Wait State Select .equ SRE = 7 ; External SRAM Enable ; XMCRA - External Memory Control Register A .equ SRW11 = 1 ; Wait state select bit upper page .equ SRW00 = 2 ; Wait state select bit lower page .equ SRW01 = 3 ; Wait state select bit lower page .equ SRL0 = 4 ; Wait state page limit .equ SRL1 = 5 ; Wait state page limit .equ SRL2 = 6 ; Wait state page limit ; XMCRB - External Memory Control Register B .equ XMM0 = 0 ; External Memory High Mask .equ XMM1 = 1 ; External Memory High Mask .equ XMM2 = 2 ; External Memory High Mask .equ XMBK = 7 ; External Memory Bus Keeper Enable ; OSCCAL - Oscillator Calibration Value .equ CAL0 = 0 ; Oscillator Calibration Value .equ CAL1 = 1 ; Oscillator Calibration Value .equ CAL2 = 2 ; Oscillator Calibration Value .equ CAL3 = 3 ; Oscillator Calibration Value .equ CAL4 = 4 ; Oscillator Calibration Value .equ CAL5 = 5 ; Oscillator Calibration Value .equ CAL6 = 6 ; Oscillator Calibration Value .equ CAL7 = 7 ; Oscillator Calibration Value ; XDIV - XTAL Divide Control Register .equ XDIV0 = 0 ; XTAl Divide Select Bit 0 .equ XDIV1 = 1 ; XTAl Divide Select Bit 1 .equ XDIV2 = 2 ; XTAl Divide Select Bit 2 .equ XDIV3 = 3 ; XTAl Divide Select Bit 3 .equ XDIV4 = 4 ; XTAl Divide Select Bit 4 .equ XDIV5 = 5 ; XTAl Divide Select Bit 5 .equ XDIV6 = 6 ; XTAl Divide Select Bit 6 .equ XDIVEN = 7 ; XTAL Divide Enable ; MCUCSR - MCU Control And Status Register .equ PORF = 0 ; Power-on reset flag .equ EXTRF = 1 ; External Reset Flag .equ BORF = 2 ; Brown-out Reset Flag .equ WDRF = 3 ; Watchdog Reset Flag .equ JTRF = 4 ; JTAG Reset Flag .equ JTD = 7 ; JTAG Interface Disable ; ***** BOOT_LOAD ******************** ; SPMCSR - Store Program Memory Control Register .equ SPMCR = SPMCSR ; For compatibility .equ SPMEN = 0 ; Store Program Memory Enable .equ PGERS = 1 ; Page Erase .equ PGWRT = 2 ; Page Write .equ BLBSET = 3 ; Boot Lock Bit Set .equ RWWSRE = 4 ; Read While Write section read enable .equ ASRE = RWWSRE ; For compatibility .equ RWWSB = 6 ; Read While Write Section Busy .equ ASB = RWWSB ; For compatibility .equ SPMIE = 7 ; SPM Interrupt Enable ; ***** JTAG ************************* ; OCDR - On-Chip Debug Related Register in I/O Memory .equ OCDR0 = 0 ; On-Chip Debug Register Bit 0 .equ OCDR1 = 1 ; On-Chip Debug Register Bit 1 .equ OCDR2 = 2 ; On-Chip Debug Register Bit 2 .equ OCDR3 = 3 ; On-Chip Debug Register Bit 3 .equ OCDR4 = 4 ; On-Chip Debug Register Bit 4 .equ OCDR5 = 5 ; On-Chip Debug Register Bit 5 .equ OCDR6 = 6 ; On-Chip Debug Register Bit 6 .equ OCDR7 = 7 ; On-Chip Debug Register Bit 7 .equ IDRD = OCDR7 ; For compatibility ; MCUCSR - MCU Control And Status Register ;.equ JTRF = 4 ; JTAG Reset Flag ;.equ JTD = 7 ; JTAG Interface Disable ; ***** MISC ************************* ; SFIOR - Special Function IO Register .equ PSR321 = 0 ; Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1 .equ PSR1 = PSR321 ; For compatibility .equ PSR2 = PSR321 ; For compatibility .equ PSR3 = PSR321 ; For compatibility .equ PSR0 = 1 ; Prescaler Reset Timer/Counter0 .equ PUD = 2 ; Pull Up Disable ;.equ ACME = 3 ; Analog Comparator Multiplexer Enable .equ TSM = 7 ; Timer/Counter Synchronization Mode ; ***** EXTERNAL_INTERRUPT *********** ; EICRA - External Interrupt Control Register A .equ ISC00 = 0 ; External Interrupt Sense Control Bit .equ ISC01 = 1 ; External Interrupt Sense Control Bit .equ ISC10 = 2 ; External Interrupt Sense Control Bit .equ ISC11 = 3 ; External Interrupt Sense Control Bit .equ ISC20 = 4 ; External Interrupt Sense Control Bit .equ ISC21 = 5 ; External Interrupt Sense Control Bit .equ ISC30 = 6 ; External Interrupt Sense Control Bit .equ ISC31 = 7 ; External Interrupt Sense Control Bit ; EICRB - External Interrupt Control Register B .equ ISC40 = 0 ; External Interrupt 7-4 Sense Control Bit .equ ISC41 = 1 ; External Interrupt 7-4 Sense Control Bit .equ ISC50 = 2 ; External Interrupt 7-4 Sense Control Bit .equ ISC51 = 3 ; External Interrupt 7-4 Sense Control Bit .equ ISC60 = 4 ; External Interrupt 7-4 Sense Control Bit .equ ISC61 = 5 ; External Interrupt 7-4 Sense Control Bit .equ ISC70 = 6 ; External Interrupt 7-4 Sense Control Bit .equ ISC71 = 7 ; External Interrupt 7-4 Sense Control Bit ; EIMSK - External Interrupt Mask Register .equ GICR = EIMSK ; For compatibility .equ GIMSK = EIMSK ; For compatibility .equ INT0 = 0 ; External Interrupt Request 0 Enable .equ INT1 = 1 ; External Interrupt Request 1 Enable .equ INT2 = 2 ; External Interrupt Request 2 Enable .equ INT3 = 3 ; External Interrupt Request 3 Enable .equ INT4 = 4 ; External Interrupt Request 4 Enable .equ INT5 = 5 ; External Interrupt Request 5 Enable .equ INT6 = 6 ; External Interrupt Request 6 Enable .equ INT7 = 7 ; External Interrupt Request 7 Enable ; EIFR - External Interrupt Flag Register .equ GIFR = EIFR ; For compatibility .equ INTF0 = 0 ; External Interrupt Flag 0 .equ INTF1 = 1 ; External Interrupt Flag 1 .equ INTF2 = 2 ; External Interrupt Flag 2 .equ INTF3 = 3 ; External Interrupt Flag 3 .equ INTF4 = 4 ; External Interrupt Flag 4 .equ INTF5 = 5 ; External Interrupt Flag 5 .equ INTF6 = 6 ; External Interrupt Flag 6 .equ INTF7 = 7 ; External Interrupt Flag 7 ; ***** EEPROM *********************** ; EEDR - EEPROM Data Register .equ EEDR0 = 0 ; EEPROM Data Register bit 0 .equ EEDR1 = 1 ; EEPROM Data Register bit 1 .equ EEDR2 = 2 ; EEPROM Data Register bit 2 .equ EEDR3 = 3 ; EEPROM Data Register bit 3 .equ EEDR4 = 4 ; EEPROM Data Register bit 4 .equ EEDR5 = 5 ; EEPROM Data Register bit 5 .equ EEDR6 = 6 ; EEPROM Data Register bit 6 .equ EEDR7 = 7 ; EEPROM Data Register bit 7 ; EECR - EEPROM Control Register .equ EERE = 0 ; EEPROM Read Enable .equ EEWE = 1 ; EEPROM Write Enable .equ EEMWE = 2 ; EEPROM Master Write Enable .equ EERIE = 3 ; EEPROM Ready Interrupt Enable ; ***** PORTA ************************ ; PORTA - Port A Data Register .equ PORTA0 = 0 ; Port A Data Register bit 0 .equ PA0 = 0 ; For compatibility .equ PORTA1 = 1 ; Port A Data Register bit 1 .equ PA1 = 1 ; For compatibility .equ PORTA2 = 2 ; Port A Data Register bit 2 .equ PA2 = 2 ; For compatibility .equ PORTA3 = 3 ; Port A Data Register bit 3 .equ PA3 = 3 ; For compatibility .equ PORTA4 = 4 ; Port A Data Register bit 4 .equ PA4 = 4 ; For compatibility .equ PORTA5 = 5 ; Port A Data Register bit 5 .equ PA5 = 5 ; For compatibility .equ PORTA6 = 6 ; Port A Data Register bit 6 .equ PA6 = 6 ; For compatibility .equ PORTA7 = 7 ; Port A Data Register bit 7 .equ PA7 = 7 ; For compatibility ; DDRA - Port A Data Direction Register .equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 .equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 .equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 .equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 .equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 .equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 .equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 .equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 ; PINA - Port A Input Pins .equ PINA0 = 0 ; Input Pins, Port A bit 0 .equ PINA1 = 1 ; Input Pins, Port A bit 1 .equ PINA2 = 2 ; Input Pins, Port A bit 2 .equ PINA3 = 3 ; Input Pins, Port A bit 3 .equ PINA4 = 4 ; Input Pins, Port A bit 4 .equ PINA5 = 5 ; Input Pins, Port A bit 5 .equ PINA6 = 6 ; Input Pins, Port A bit 6 .equ PINA7 = 7 ; Input Pins, Port A bit 7 ; ***** PORTB ************************ ; PORTB - Port B Data Register .equ PORTB0 = 0 ; Port B Data Register bit 0 .equ PB0 = 0 ; For compatibility .equ PORTB1 = 1 ; Port B Data Register bit 1 .equ PB1 = 1 ; For compatibility .equ PORTB2 = 2 ; Port B Data Register bit 2 .equ PB2 = 2 ; For compatibility .equ PORTB3 = 3 ; Port B Data Register bit 3 .equ PB3 = 3 ; For compatibility .equ PORTB4 = 4 ; Port B Data Register bit 4 .equ PB4 = 4 ; For compatibility .equ PORTB5 = 5 ; Port B Data Register bit 5 .equ PB5 = 5 ; For compatibility .equ PORTB6 = 6 ; Port B Data Register bit 6 .equ PB6 = 6 ; For compatibility .equ PORTB7 = 7 ; Port B Data Register bit 7 .equ PB7 = 7 ; For compatibility ; DDRB - Port B Data Direction Register .equ DDB0 = 0 ; Port B Data Direction Register bit 0 .equ DDB1 = 1 ; Port B Data Direction Register bit 1 .equ DDB2 = 2 ; Port B Data Direction Register bit 2 .equ DDB3 = 3 ; Port B Data Direction Register bit 3 .equ DDB4 = 4 ; Port B Data Direction Register bit 4 .equ DDB5 = 5 ; Port B Data Direction Register bit 5 .equ DDB6 = 6 ; Port B Data Direction Register bit 6 .equ DDB7 = 7 ; Port B Data Direction Register bit 7 ; PINB - Port B Input Pins .equ PINB0 = 0 ; Port B Input Pins bit 0 .equ PINB1 = 1 ; Port B Input Pins bit 1 .equ PINB2 = 2 ; Port B Input Pins bit 2 .equ PINB3 = 3 ; Port B Input Pins bit 3 .equ PINB4 = 4 ; Port B Input Pins bit 4 .equ PINB5 = 5 ; Port B Input Pins bit 5 .equ PINB6 = 6 ; Port B Input Pins bit 6 .equ PINB7 = 7 ; Port B Input Pins bit 7 ; ***** PORTC ************************ ; PORTC - Port C Data Register .equ PORTC0 = 0 ; Port C Data Register bit 0 .equ PC0 = 0 ; For compatibility .equ PORTC1 = 1 ; Port C Data Register bit 1 .equ PC1 = 1 ; For compatibility .equ PORTC2 = 2 ; Port C Data Register bit 2 .equ PC2 = 2 ; For compatibility .equ PORTC3 = 3 ; Port C Data Register bit 3 .equ PC3 = 3 ; For compatibility .equ PORTC4 = 4 ; Port C Data Register bit 4 .equ PC4 = 4 ; For compatibility .equ PORTC5 = 5 ; Port C Data Register bit 5 .equ PC5 = 5 ; For compatibility .equ PORTC6 = 6 ; Port C Data Register bit 6 .equ PC6 = 6 ; For compatibility .equ PORTC7 = 7 ; Port C Data Register bit 7 .equ PC7 = 7 ; For compatibility ; DDRC - Port C Data Direction Register .equ DDC0 = 0 ; Port C Data Direction Register bit 0 .equ DDC1 = 1 ; Port C Data Direction Register bit 1 .equ DDC2 = 2 ; Port C Data Direction Register bit 2 .equ DDC3 = 3 ; Port C Data Direction Register bit 3 .equ DDC4 = 4 ; Port C Data Direction Register bit 4 .equ DDC5 = 5 ; Port C Data Direction Register bit 5 .equ DDC6 = 6 ; Port C Data Direction Register bit 6 .equ DDC7 = 7 ; Port C Data Direction Register bit 7 ; PINC - Port C Input Pins .equ PINC0 = 0 ; Port C Input Pins bit 0 .equ PINC1 = 1 ; Port C Input Pins bit 1 .equ PINC2 = 2 ; Port C Input Pins bit 2 .equ PINC3 = 3 ; Port C Input Pins bit 3 .equ PINC4 = 4 ; Port C Input Pins bit 4 .equ PINC5 = 5 ; Port C Input Pins bit 5 .equ PINC6 = 6 ; Port C Input Pins bit 6 .equ PINC7 = 7 ; Port C Input Pins bit 7 ; ***** PORTD ************************ ; PORTD - Port D Data Register .equ PORTD0 = 0 ; Port D Data Register bit 0 .equ PD0 = 0 ; For compatibility .equ PORTD1 = 1 ; Port D Data Register bit 1 .equ PD1 = 1 ; For compatibility .equ PORTD2 = 2 ; Port D Data Register bit 2 .equ PD2 = 2 ; For compatibility .equ PORTD3 = 3 ; Port D Data Register bit 3 .equ PD3 = 3 ; For compatibility .equ PORTD4 = 4 ; Port D Data Register bit 4 .equ PD4 = 4 ; For compatibility .equ PORTD5 = 5 ; Port D Data Register bit 5 .equ PD5 = 5 ; For compatibility .equ PORTD6 = 6 ; Port D Data Register bit 6 .equ PD6 = 6 ; For compatibility .equ PORTD7 = 7 ; Port D Data Register bit 7 .equ PD7 = 7 ; For compatibility ; DDRD - Port D Data Direction Register .equ DDD0 = 0 ; Port D Data Direction Register bit 0 .equ DDD1 = 1 ; Port D Data Direction Register bit 1 .equ DDD2 = 2 ; Port D Data Direction Register bit 2 .equ DDD3 = 3 ; Port D Data Direction Register bit 3 .equ DDD4 = 4 ; Port D Data Direction Register bit 4 .equ DDD5 = 5 ; Port D Data Direction Register bit 5 .equ DDD6 = 6 ; Port D Data Direction Register bit 6 .equ DDD7 = 7 ; Port D Data Direction Register bit 7 ; PIND - Port D Input Pins .equ PIND0 = 0 ; Port D Input Pins bit 0 .equ PIND1 = 1 ; Port D Input Pins bit 1 .equ PIND2 = 2 ; Port D Input Pins bit 2 .equ PIND3 = 3 ; Port D Input Pins bit 3 .equ PIND4 = 4 ; Port D Input Pins bit 4 .equ PIND5 = 5 ; Port D Input Pins bit 5 .equ PIND6 = 6 ; Port D Input Pins bit 6 .equ PIND7 = 7 ; Port D Input Pins bit 7 ; ***** PORTE ************************ ; PORTE - Data Register, Port E .equ PORTE0 = 0 ; .equ PE0 = 0 ; For compatibility .equ PORTE1 = 1 ; .equ PE1 = 1 ; For compatibility .equ PORTE2 = 2 ; .equ PE2 = 2 ; For compatibility .equ PORTE3 = 3 ; .equ PE3 = 3 ; For compatibility .equ PORTE4 = 4 ; .equ PE4 = 4 ; For compatibility .equ PORTE5 = 5 ; .equ PE5 = 5 ; For compatibility .equ PORTE6 = 6 ; .equ PE6 = 6 ; For compatibility .equ PORTE7 = 7 ; .equ PE7 = 7 ; For compatibility ; DDRE - Data Direction Register, Port E .equ DDE0 = 0 ; .equ DDE1 = 1 ; .equ DDE2 = 2 ; .equ DDE3 = 3 ; .equ DDE4 = 4 ; .equ DDE5 = 5 ; .equ DDE6 = 6 ; .equ DDE7 = 7 ; ; PINE - Input Pins, Port E .equ PINE0 = 0 ; .equ PINE1 = 1 ; .equ PINE2 = 2 ; .equ PINE3 = 3 ; .equ PINE4 = 4 ; .equ PINE5 = 5 ; .equ PINE6 = 6 ; .equ PINE7 = 7 ; ; ***** PORTF ************************ ; PORTF - Data Register, Port F .equ PORTF0 = 0 ; .equ PF0 = 0 ; For compatibility .equ PORTF1 = 1 ; .equ PF1 = 1 ; For compatibility .equ PORTF2 = 2 ; .equ PF2 = 2 ; For compatibility .equ PORTF3 = 3 ; .equ PF3 = 3 ; For compatibility .equ PORTF4 = 4 ; .equ PF4 = 4 ; For compatibility .equ PORTF5 = 5 ; .equ PF5 = 5 ; For compatibility .equ PORTF6 = 6 ; .equ PF6 = 6 ; For compatibility .equ PORTF7 = 7 ; .equ PF7 = 7 ; For compatibility ; DDRF - Data Direction Register, Port F .equ DDF0 = 0 ; .equ DDF1 = 1 ; .equ DDF2 = 2 ; .equ DDF3 = 3 ; .equ DDF4 = 4 ; .equ DDF5 = 5 ; .equ DDF6 = 6 ; .equ DDF7 = 7 ; ; PINF - Input Pins, Port F .equ PINF0 = 0 ; .equ PINF1 = 1 ; .equ PINF2 = 2 ; .equ PINF3 = 3 ; .equ PINF4 = 4 ; .equ PINF5 = 5 ; .equ PINF6 = 6 ; .equ PINF7 = 7 ; ; ***** PORTG ************************ ; PORTG - Data Register, Port G .equ PORTG0 = 0 ; .equ PG0 = 0 ; For compatibility .equ PORTG1 = 1 ; .equ PG1 = 1 ; For compatibility .equ PORTG2 = 2 ; .equ PG2 = 2 ; For compatibility .equ PORTG3 = 3 ; .equ PG3 = 3 ; For compatibility .equ PORTG4 = 4 ; .equ PG4 = 4 ; For compatibility ; DDRG - Data Direction Register, Port G .equ DDG0 = 0 ; .equ DDG1 = 1 ; .equ DDG2 = 2 ; .equ DDG3 = 3 ; .equ DDG4 = 4 ; ; PING - Input Pins, Port G .equ PING0 = 0 ; .equ PING1 = 1 ; .equ PING2 = 2 ; .equ PING3 = 3 ; .equ PING4 = 4 ; ; ***** TIMER_COUNTER_0 ************** ; TCCR0 - Timer/Counter Control Register .equ CS00 = 0 ; Clock Select 0 .equ CS01 = 1 ; Clock Select 1 .equ CS02 = 2 ; Clock Select 2 .equ WGM01 = 3 ; Waveform Generation Mode 1 .equ CTC0 = WGM01 ; For compatibility .equ COM00 = 4 ; Compare match Output Mode 0 .equ COM01 = 5 ; Compare Match Output Mode 1 .equ WGM00 = 6 ; Waveform Generation Mode 0 .equ PWM0 = WGM00 ; For compatibility .equ FOC0 = 7 ; Force Output Compare ; TCNT0 - Timer/Counter Register .equ TCNT0_0 = 0 ; .equ TCNT0_1 = 1 ; .equ TCNT0_2 = 2 ; .equ TCNT0_3 = 3 ; .equ TCNT0_4 = 4 ; .equ TCNT0_5 = 5 ; .equ TCNT0_6 = 6 ; .equ TCNT0_7 = 7 ; ; OCR0 - Output Compare Register .equ OCR0_0 = 0 ; .equ OCR0_1 = 1 ; .equ OCR0_2 = 2 ; .equ OCR0_3 = 3 ; .equ OCR0_4 = 4 ; .equ OCR0_5 = 5 ; .equ OCR0_6 = 6 ; .equ OCR0_7 = 7 ; ; ASSR - Asynchronus Status Register .equ TCR0UB = 0 ; Timer/Counter Control Register 0 Update Busy .equ OCR0UB = 1 ; Output Compare register 0 Busy .equ TCN0UB = 2 ; Timer/Counter0 Update Busy .equ AS0 = 3 ; Asynchronus Timer/Counter 0 ; TIMSK - Timer/Counter Interrupt Mask Register .equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable .equ OCIE0 = 1 ; Timer/Counter0 Output Compare Match Interrupt register ; TIFR - Timer/Counter Interrupt Flag register .equ TOV0 = 0 ; Timer/Counter0 Overflow Flag .equ OCF0 = 1 ; Output Compare Flag 0 ; SFIOR - Special Function IO Register ;.equ PSR0 = 1 ; Prescaler Reset Timer/Counter0 ;.equ TSM = 7 ; Timer/Counter Synchronization Mode ; ***** TIMER_COUNTER_1 ************** ; TIMSK - Timer/Counter Interrupt Mask Register .equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable .equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable .equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable .equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable ; ETIMSK - Extended Timer/Counter Interrupt Mask Register .equ OCIE1C = 0 ; Timer/Counter 1, Output Compare Match C Interrupt Enable ; TIFR - Timer/Counter Interrupt Flag register .equ TOV1 = 2 ; Timer/Counter1 Overflow Flag .equ OCF1B = 3 ; Output Compare Flag 1B .equ OCF1A = 4 ; Output Compare Flag 1A .equ ICF1 = 5 ; Input Capture Flag 1 ; ETIFR - Extended Timer/Counter Interrupt Flag register .equ OCF1C = 0 ; Timer/Counter 1, Output Compare C Match Flag ; SFIOR - Special Function IO Register ;.equ PSR321 = 0 ; Prescaler Reset, T/C3, T/C2, T/C1 ;.equ TSM = 7 ; Timer/Counter Synchronization Mode ; TCCR1A - Timer/Counter1 Control Register A .equ WGM10 = 0 ; Waveform Generation Mode Bit 0 .equ PWM10 = WGM10 ; For compatibility .equ WGM11 = 1 ; Waveform Generation Mode Bit 1 .equ PWM11 = WGM11 ; For compatibility .equ COM1C0 = 2 ; Compare Output Mode 1C, bit 0 .equ COM1C1 = 3 ; Compare Output Mode 1C, bit 1 .equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 .equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 .equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0 .equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 ; TCCR1B - Timer/Counter1 Control Register B .equ CS10 = 0 ; Clock Select bit 0 .equ CS11 = 1 ; Clock Select 1 bit 1 .equ CS12 = 2 ; Clock Select1 bit 2 .equ WGM12 = 3 ; Waveform Generation Mode .equ CTC10 = WGM12 ; For compatibility .equ WGM13 = 4 ; Waveform Generation Mode .equ CTC11 = WGM13 ; For compatibility .equ ICES1 = 6 ; Input Capture 1 Edge Select .equ ICNC1 = 7 ; Input Capture 1 Noise Canceler ; TCCR1C - Timer/Counter1 Control Register C .equ FOC1C = 5 ; Force Output Compare for channel C .equ FOC1B = 6 ; Force Output Compare for channel B .equ FOC1A = 7 ; Force Output Compare for channel A ; ***** TIMER_COUNTER_2 ************** ; TCCR2 - Timer/Counter Control Register .equ CS20 = 0 ; Clock Select .equ CS21 = 1 ; Clock Select .equ CS22 = 2 ; Clock Select .equ WGM21 = 3 ; Waveform Generation Mode .equ CTC2 = WGM21 ; For compatibility .equ COM20 = 4 ; Compare Match Output Mode .equ COM21 = 5 ; Compare Match Output Mode .equ WGM20 = 6 ; Wafeform Generation Mode .equ PWM2 = WGM20 ; For compatibility .equ FOC2 = 7 ; Force Output Compare ; TCNT2 - Timer/Counter Register .equ TCNT2_0 = 0 ; Timer/Counter Register Bit 0 .equ TCNT2_1 = 1 ; Timer/Counter Register Bit 1 .equ TCNT2_2 = 2 ; Timer/Counter Register Bit 2 .equ TCNT2_3 = 3 ; Timer/Counter Register Bit 3 .equ TCNT2_4 = 4 ; Timer/Counter Register Bit 4 .equ TCNT2_5 = 5 ; Timer/Counter Register Bit 5 .equ TCNT2_6 = 6 ; Timer/Counter Register Bit 6 .equ TCNT2_7 = 7 ; Timer/Counter Register Bit 7 ; OCR2 - Output Compare Register .equ OCR2_0 = 0 ; Output Compare Register Bit 0 .equ OCR2_1 = 1 ; Output Compare Register Bit 1 .equ OCR2_2 = 2 ; Output Compare Register Bit 2 .equ OCR2_3 = 3 ; Output Compare Register Bit 3 .equ OCR2_4 = 4 ; Output Compare Register Bit 4 .equ OCR2_5 = 5 ; Output Compare Register Bit 5 .equ OCR2_6 = 6 ; Output Compare Register Bit 6 .equ OCR2_7 = 7 ; Output Compare Register Bit 7 ; TIMSK - .equ TOIE2 = 6 ; .equ OCIE2 = 7 ; ; TIFR - Timer/Counter Interrupt Flag Register .equ TOV2 = 6 ; Timer/Counter2 Overflow Flag .equ OCF2 = 7 ; Output Compare Flag 2 ; ***** TIMER_COUNTER_3 ************** ; ETIMSK - Extended Timer/Counter Interrupt Mask Register .equ OCIE3C = 1 ; Timer/Counter3, Output Compare Match Interrupt Enable .equ TOIE3 = 2 ; Timer/Counter3 Overflow Interrupt Enable .equ OCIE3B = 3 ; Timer/Counter3 Output CompareB Match Interrupt Enable .equ OCIE3A = 4 ; Timer/Counter3 Output CompareA Match Interrupt Enable .equ TICIE3 = 5 ; Timer/Counter3 Input Capture Interrupt Enable ; ETIFR - Extended Timer/Counter Interrupt Flag register .equ OCF3C = 1 ; Timer/Counter3 Output Compare C Match Flag .equ TOV3 = 2 ; Timer/Counter3 Overflow Flag .equ OCF3B = 3 ; Output Compare Flag 1B .equ OCF3A = 4 ; Output Compare Flag 1A .equ ICF3 = 5 ; Input Capture Flag 1 ; SFIOR - Special Function IO Register ;.equ PSR321 = 0 ; Prescaler Reset, T/C3, T/C2, T/C1 ;.equ PSR1 = PSR321 ; For compatibility ;.equ PSR2 = PSR321 ; For compatibility ;.equ TSM = 7 ; Timer/Counter Synchronization Mode ; TCCR3A - Timer/Counter3 Control Register A .equ WGM30 = 0 ; Waveform Generation Mode Bit 0 .equ PWM30 = WGM30 ; For compatibility .equ WGM31 = 1 ; Waveform Generation Mode Bit 1 .equ PWM31 = WGM31 ; For compatibility .equ COM3C0 = 2 ; Compare Output Mode 3C, bit 0 .equ COM3C1 = 3 ; Compare Output Mode 3C, bit 1 .equ COM3B0 = 4 ; Compare Output Mode 3B, bit 0 .equ COM3B1 = 5 ; Compare Output Mode 3B, bit 1 .equ COM3A0 = 6 ; Comparet Ouput Mode 3A, bit 0 .equ COM3A1 = 7 ; Compare Output Mode 3A, bit 1 ; TCCR3B - Timer/Counter3 Control Register B .equ CS30 = 0 ; Clock Select 3 bit 0 .equ CS31 = 1 ; Clock Select 3 bit 1 .equ CS32 = 2 ; Clock Select3 bit 2 .equ WGM32 = 3 ; Waveform Generation Mode .equ CTC30 = WGM32 ; For compatibility .equ WGM33 = 4 ; Waveform Generation Mode .equ CTC31 = WGM33 ; For compatibility .equ ICES3 = 6 ; Input Capture 3 Edge Select .equ ICNC3 = 7 ; Input Capture 3 Noise Canceler ; TCCR3C - Timer/Counter3 Control Register C .equ FOC3C = 5 ; Force Output Compare for channel C .equ FOC3B = 6 ; Force Output Compare for channel B .equ FOC3A = 7 ; Force Output Compare for channel A ; TCNT3L - Timer/Counter3 Low Byte .equ TCN3L0 = 0 ; Timer/Counter 3 bit 0 .equ TCN3L1 = 1 ; Timer/Counter 3 bit 1 .equ TCN3L2 = 2 ; Timer/Counter 3 bit 2 .equ TCN3L3 = 3 ; Timer/Counter 3 bit 3 .equ TCN3L4 = 4 ; Timer/Counter 3 bit 4 .equ TCN3L5 = 5 ; Timer/Counter 3 bit 5 .equ TCN3L6 = 6 ; Timer/Counter 3 bit 6 .equ TCN3L7 = 7 ; Timer/Counter 3 bit 7 ; ***** WATCHDOG ********************* ; WDTCR - Watchdog Timer Control Register .equ WDTCSR = WDTCR ; For compatibility .equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 .equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 .equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 .equ WDE = 3 ; Watch Dog Enable .equ WDCE = 4 ; Watchdog Change Enable .equ WDTOE = WDCE ; For compatibility ; ***** LOCKSBITS ******************************************************** .equ LB1 = 0 ; Lock bit .equ LB2 = 1 ; Lock bit .equ BLB01 = 2 ; Boot Lock bit .equ BLB02 = 3 ; Boot Lock bit .equ BLB11 = 4 ; Boot lock bit .equ BLB12 = 5 ; Boot lock bit ; ***** FUSES ************************************************************ ; LOW fuse bits .equ CKSEL0 = 0 ; Select Clock Source .equ CKSEL1 = 1 ; Select Clock Source .equ CKSEL2 = 2 ; Select Clock Source .equ CKSEL3 = 3 ; Select Clock Source .equ SUT0 = 4 ; Select start-up time .equ SUT1 = 5 ; Select start-up time .equ BODEN = 6 ; Brown out detector enable .equ BODLEVEL = 7 ; Brown out detector trigger level ; HIGH fuse bits .equ BOOTRST = 0 ; Select Reset Vector .equ BOOTSZ0 = 1 ; Select Boot Size .equ BOOTSZ1 = 2 ; Select Boot Size .equ EESAVE = 3 ; EEPROM memory is preserved through chip erase .equ CKOPT = 4 ; Oscillator Options .equ SPIEN = 5 ; Enable Serial programming and Data Downloading .equ JTAGEN = 6 ; Enable JTAG .equ OCDEN = 7 ; Enable OCD ; EXTENDED fuse bits .equ WDTON = 0 ; Watchdog timer always on .equ CompMode = 1 ; Compabillity mode ; ***** CPU REGISTER DEFINITIONS ***************************************** .def XH = r27 .def XL = r26 .def YH = r29 .def YL = r28 .def ZH = r31 .def ZL = r30 ; ***** DATA MEMORY DECLARATIONS ***************************************** .equ FLASHEND = 0x7fff ; Note: Word address .equ IOEND = 0x00ff .equ SRAM_START = 0x0100 .equ SRAM_SIZE = 4096 .equ RAMEND = 0x10ff .equ XRAMEND = 0xffff .equ E2END = 0x07ff .equ EEPROMEND = 0x07ff .equ EEADRBITS = 11 #pragma AVRPART MEMORY PROG_FLASH 65536 #pragma AVRPART MEMORY EEPROM 2048 #pragma AVRPART MEMORY INT_SRAM SIZE 4096 #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 ; ***** BOOTLOADER DECLARATIONS ****************************************** .equ NRWW_START_ADDR = 0x7000 .equ NRWW_STOP_ADDR = 0x7fff .equ RWW_START_ADDR = 0x0 .equ RWW_STOP_ADDR = 0x6fff .equ PAGESIZE = 128 .equ FIRSTBOOTSTART = 0x7e00 .equ SECONDBOOTSTART = 0x7c00 .equ THIRDBOOTSTART = 0x7800 .equ FOURTHBOOTSTART = 0x7000 .equ SMALLBOOTSTART = FIRSTBOOTSTART .equ LARGEBOOTSTART = FOURTHBOOTSTART ; ***** INTERRUPT VECTORS ************************************************ .equ INT0addr = 0x0002 ; External Interrupt Request 0 .equ INT1addr = 0x0004 ; External Interrupt Request 1 .equ INT2addr = 0x0006 ; External Interrupt Request 2 .equ INT3addr = 0x0008 ; External Interrupt Request 3 .equ INT4addr = 0x000a ; External Interrupt Request 4 .equ INT5addr = 0x000c ; External Interrupt Request 5 .equ INT6addr = 0x000e ; External Interrupt Request 6 .equ INT7addr = 0x0010 ; External Interrupt Request 7 .equ OC2addr = 0x0012 ; Timer/Counter2 Compare Match .equ OVF2addr = 0x0014 ; Timer/Counter2 Overflow .equ ICP1addr = 0x0016 ; Timer/Counter1 Capture Event .equ OC1Aaddr = 0x0018 ; Timer/Counter1 Compare Match A .equ OC1Baddr = 0x001a ; Timer/Counter Compare Match B .equ OVF1addr = 0x001c ; Timer/Counter1 Overflow .equ OC0addr = 0x001e ; Timer/Counter0 Compare Match .equ OVF0addr = 0x0020 ; Timer/Counter0 Overflow .equ SPIaddr = 0x0022 ; SPI Serial Transfer Complete .equ URXC0addr = 0x0024 ; USART0, Rx Complete .equ UDRE0addr = 0x0026 ; USART0 Data Register Empty .equ UTXC0addr = 0x0028 ; USART0, Tx Complete .equ ADCCaddr = 0x002a ; ADC Conversion Complete .equ ERDYaddr = 0x002c ; EEPROM Ready .equ ACIaddr = 0x002e ; Analog Comparator .equ OC1Caddr = 0x0030 ; Timer/Counter1 Compare Match C .equ ICP3addr = 0x0032 ; Timer/Counter3 Capture Event .equ OC3Aaddr = 0x0034 ; Timer/Counter3 Compare Match A .equ OC3Baddr = 0x0036 ; Timer/Counter3 Compare Match B .equ OC3Caddr = 0x0038 ; Timer/Counter3 Compare Match C .equ OVF3addr = 0x003a ; Timer/Counter3 Overflow .equ URXC1addr = 0x003c ; USART1, Rx Complete .equ UDRE1addr = 0x003e ; USART1, Data Register Empty .equ UTXC1addr = 0x0040 ; USART1, Tx Complete .equ TWIaddr = 0x0042 ; 2-wire Serial Interface .equ SPMRaddr = 0x0044 ; Store Program Memory Read .equ INT_VECTORS_SIZE = 70 ; size in words #endif /* _M64DEF_INC_ */ ; ***** END OF FILE ****************************************************** /* Copyright (c) 2002, Steinar Haugen All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom64.h,v 1.14.2.5 2008/10/17 23:27:49 arcanum Exp $ */ /* avr/iom64.h - defines for ATmega64 As of 2002-11-23: - This should be up to date with data sheet Rev. 2490C-AVR-09/02 */ #ifndef _AVR_IOM64_H_ #define _AVR_IOM64_H_ 1 /* This file should only be included from <avr/io.h>, never directly. */ #ifndef _AVR_IO_H_ # error "Include <avr/io.h> instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom64.h" #else # error "Attempt to include more than one <avr/ioXXX.h> file." #endif /* I/O registers */ /* Input Pins, Port F */ #define PINF _SFR_IO8(0x00) /* Input Pins, Port E */ #define PINE _SFR_IO8(0x01) /* Data Direction Register, Port E */ #define DDRE _SFR_IO8(0x02) /* Data Register, Port E */ #define PORTE _SFR_IO8(0x03) /* ADC Data Register */ #define ADCW _SFR_IO16(0x04) /* for backwards compatibility */ #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) /* ADC Control and Status Register A */ #define ADCSR _SFR_IO8(0x06) /* for backwards compatibility */ #define ADCSRA _SFR_IO8(0x06) /* ADC Multiplexer select */ #define ADMUX _SFR_IO8(0x07) /* Analog Comparator Control and Status Register */ #define ACSR _SFR_IO8(0x08) /* USART0 Baud Rate Register Low */ #define UBRR0L _SFR_IO8(0x09) /* USART0 Control and Status Register B */ #define UCSR0B _SFR_IO8(0x0A) /* USART0 Control and Status Register A */ #define UCSR0A _SFR_IO8(0x0B) /* USART0 I/O Data Register */ #define UDR0 _SFR_IO8(0x0C) /* SPI Control Register */ #define SPCR _SFR_IO8(0x0D) /* SPI Status Register */ #define SPSR _SFR_IO8(0x0E) /* SPI I/O Data Register */ #define SPDR _SFR_IO8(0x0F) /* Input Pins, Port D */ #define PIND _SFR_IO8(0x10) /* Data Direction Register, Port D */ #define DDRD _SFR_IO8(0x11) /* Data Register, Port D */ #define PORTD _SFR_IO8(0x12) /* Input Pins, Port C */ #define PINC _SFR_IO8(0x13) /* Data Direction Register, Port C */ #define DDRC _SFR_IO8(0x14) /* Data Register, Port C */ #define PORTC _SFR_IO8(0x15) /* Input Pins, Port B */ #define PINB _SFR_IO8(0x16) /* Data Direction Register, Port B */ #define DDRB _SFR_IO8(0x17) /* Data Register, Port B */ #define PORTB _SFR_IO8(0x18) /* Input Pins, Port A */ #define PINA _SFR_IO8(0x19) /* Data Direction Register, Port A */ #define DDRA _SFR_IO8(0x1A) /* Data Register, Port A */ #define PORTA _SFR_IO8(0x1B) /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEARH _SFR_IO8(0x1F) /* Special Function I/O Register */ #define SFIOR _SFR_IO8(0x20) /* Watchdog Timer Control Register */ #define WDTCR _SFR_IO8(0x21) /* On-chip Debug Register */ #define OCDR _SFR_IO8(0x22) /* Timer2 Output Compare Register */ #define OCR2 _SFR_IO8(0x23) /* Timer/Counter 2 */ #define TCNT2 _SFR_IO8(0x24) /* Timer/Counter 2 Control register */ #define TCCR2 _SFR_IO8(0x25) /* T/C 1 Input Capture Register */ #define ICR1 _SFR_IO16(0x26) #define ICR1L _SFR_IO8(0x26) #define ICR1H _SFR_IO8(0x27) /* Timer/Counter1 Output Compare Register B */ #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) /* Timer/Counter1 Output Compare Register A */ #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) /* Timer/Counter 1 */ #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) /* Timer/Counter 1 Control and Status Register */ #define TCCR1B _SFR_IO8(0x2E) /* Timer/Counter 1 Control Register */ #define TCCR1A _SFR_IO8(0x2F) /* Timer/Counter 0 Asynchronous Control & Status Register */ #define ASSR _SFR_IO8(0x30) /* Output Compare Register 0 */ #define OCR0 _SFR_IO8(0x31) /* Timer/Counter 0 */ #define TCNT0 _SFR_IO8(0x32) /* Timer/Counter 0 Control Register */ #define TCCR0 _SFR_IO8(0x33) /* MCU Status Register */ #define MCUSR _SFR_IO8(0x34) /* for backwards compatibility */ #define MCUCSR _SFR_IO8(0x34) /* MCU general Control Register */ #define MCUCR _SFR_IO8(0x35) /* Timer/Counter Interrupt Flag Register */ #define TIFR _SFR_IO8(0x36) /* Timer/Counter Interrupt MaSK register */ #define TIMSK _SFR_IO8(0x37) /* External Interrupt Flag Register */ #define EIFR _SFR_IO8(0x38) /* External Interrupt MaSK register */ #define EIMSK _SFR_IO8(0x39) /* External Interrupt Control Register B */ #define EICRB _SFR_IO8(0x3A) /* XDIV Divide control register */ #define XDIV _SFR_IO8(0x3C) /* 0x3D..0x3E SP */ /* 0x3F SREG */ /* Extended I/O registers */ /* Data Direction Register, Port F */ #define DDRF _SFR_MEM8(0x61) /* Data Register, Port F */ #define PORTF _SFR_MEM8(0x62) /* Input Pins, Port G */ #define PING _SFR_MEM8(0x63) /* Data Direction Register, Port G */ #define DDRG _SFR_MEM8(0x64) /* Data Register, Port G */ #define PORTG _SFR_MEM8(0x65) /* Store Program Memory Control and Status Register */ #define SPMCR _SFR_MEM8(0x68) #define SPMCSR _SFR_MEM8(0x68) /* for backwards compatibility with m128*/ /* External Interrupt Control Register A */ #define EICRA _SFR_MEM8(0x6A) /* External Memory Control Register B */ #define XMCRB _SFR_MEM8(0x6C) /* External Memory Control Register A */ #define XMCRA _SFR_MEM8(0x6D) /* Oscillator Calibration Register */ #define OSCCAL _SFR_MEM8(0x6F) /* 2-wire Serial Interface Bit Rate Register */ #define TWBR _SFR_MEM8(0x70) /* 2-wire Serial Interface Status Register */ #define TWSR _SFR_MEM8(0x71) /* 2-wire Serial Interface Address Register */ #define TWAR _SFR_MEM8(0x72) /* 2-wire Serial Interface Data Register */ #define TWDR _SFR_MEM8(0x73) /* 2-wire Serial Interface Control Register */ #define TWCR _SFR_MEM8(0x74) /* Time Counter 1 Output Compare Register C */ #define OCR1C _SFR_MEM16(0x78) #define OCR1CL _SFR_MEM8(0x78) #define OCR1CH _SFR_MEM8(0x79) /* Timer/Counter 1 Control Register C */ #define TCCR1C _SFR_MEM8(0x7A) /* Extended Timer Interrupt Flag Register */ #define ETIFR _SFR_MEM8(0x7C) /* Extended Timer Interrupt Mask Register */ #define ETIMSK _SFR_MEM8(0x7D) /* Timer/Counter 3 Input Capture Register */ #define ICR3 _SFR_MEM16(0x80) #define ICR3L _SFR_MEM8(0x80) #define ICR3H _SFR_MEM8(0x81) /* Timer/Counter 3 Output Compare Register C */ #define OCR3C _SFR_MEM16(0x82) #define OCR3CL _SFR_MEM8(0x82) #define OCR3CH _SFR_MEM8(0x83) /* Timer/Counter 3 Output Compare Register B */ #define OCR3B _SFR_MEM16(0x84) #define OCR3BL _SFR_MEM8(0x84) #define OCR3BH _SFR_MEM8(0x85) /* Timer/Counter 3 Output Compare Register A */ #define OCR3A _SFR_MEM16(0x86) #define OCR3AL _SFR_MEM8(0x86) #define OCR3AH _SFR_MEM8(0x87) /* Timer/Counter 3 Counter Register */ #define TCNT3 _SFR_MEM16(0x88) #define TCNT3L _SFR_MEM8(0x88) #define TCNT3H _SFR_MEM8(0x89) /* Timer/Counter 3 Control Register B */ #define TCCR3B _SFR_MEM8(0x8A) /* Timer/Counter 3 Control Register A */ #define TCCR3A _SFR_MEM8(0x8B) /* Timer/Counter 3 Control Register C */ #define TCCR3C _SFR_MEM8(0x8C) /* ADC Control and Status Register B */ #define ADCSRB _SFR_MEM8(0x8E) /* USART0 Baud Rate Register High */ #define UBRR0H _SFR_MEM8(0x90) /* USART0 Control and Status Register C */ #define UCSR0C _SFR_MEM8(0x95) /* USART1 Baud Rate Register High */ #define UBRR1H _SFR_MEM8(0x98) /* USART1 Baud Rate Register Low*/ #define UBRR1L _SFR_MEM8(0x99) /* USART1 Control and Status Register B */ #define UCSR1B _SFR_MEM8(0x9A) /* USART1 Control and Status Register A */ #define UCSR1A _SFR_MEM8(0x9B) /* USART1 I/O Data Register */ #define UDR1 _SFR_MEM8(0x9C) /* USART1 Control and Status Register C */ #define UCSR1C _SFR_MEM8(0x9D) /* Interrupt vectors */ /* External Interrupt Request 0 */ #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt Request 1 */ #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* External Interrupt Request 2 */ #define INT2_vect _VECTOR(3) #define SIG_INTERRUPT2 _VECTOR(3) /* External Interrupt Request 3 */ #define INT3_vect _VECTOR(4) #define SIG_INTERRUPT3 _VECTOR(4) /* External Interrupt Request 4 */ #define INT4_vect _VECTOR(5) #define SIG_INTERRUPT4 _VECTOR(5) /* External Interrupt Request 5 */ #define INT5_vect _VECTOR(6) #define SIG_INTERRUPT5 _VECTOR(6) /* External Interrupt Request 6 */ #define INT6_vect _VECTOR(7) #define SIG_INTERRUPT6 _VECTOR(7) /* External Interrupt Request 7 */ #define INT7_vect _VECTOR(8) #define SIG_INTERRUPT7 _VECTOR(8) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect _VECTOR(9) #define SIG_OUTPUT_COMPARE2 _VECTOR(9) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect _VECTOR(10) #define SIG_OVERFLOW2 _VECTOR(10) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect _VECTOR(11) #define SIG_INPUT_CAPTURE1 _VECTOR(11) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect _VECTOR(12) #define SIG_OUTPUT_COMPARE1A _VECTOR(12) /* Timer/Counter Compare Match B */ #define TIMER1_COMPB_vect _VECTOR(13) #define SIG_OUTPUT_COMPARE1B _VECTOR(13) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect _VECTOR(14) #define SIG_OVERFLOW1 _VECTOR(14) /* Timer/Counter0 Compare Match */ #define TIMER0_COMP_vect _VECTOR(15) #define SIG_OUTPUT_COMPARE0 _VECTOR(15) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect _VECTOR(16) #define SIG_OVERFLOW0 _VECTOR(16) /* SPI Serial Transfer Complete */ #define SPI_STC_vect _VECTOR(17) #define SIG_SPI _VECTOR(17) /* USART0, Rx Complete */ #define USART0_RX_vect _VECTOR(18) #define SIG_UART0_RECV _VECTOR(18) /* USART0 Data Register Empty */ #define USART0_UDRE_vect _VECTOR(19) #define SIG_UART0_DATA _VECTOR(19) /* USART0, Tx Complete */ #define USART0_TX_vect _VECTOR(20) #define SIG_UART0_TRANS _VECTOR(20) /* ADC Conversion Complete */ #define ADC_vect _VECTOR(21) #define SIG_ADC _VECTOR(21) /* EEPROM Ready */ #define EE_READY_vect _VECTOR(22) #define SIG_EEPROM_READY _VECTOR(22) /* Analog Comparator */ #define ANALOG_COMP_vect _VECTOR(23) #define SIG_COMPARATOR _VECTOR(23) /* Timer/Counter1 Compare Match C */ #define TIMER1_COMPC_vect _VECTOR(24) #define SIG_OUTPUT_COMPARE1C _VECTOR(24) /* Timer/Counter3 Capture Event */ #define TIMER3_CAPT_vect _VECTOR(25) #define SIG_INPUT_CAPTURE3 _VECTOR(25) /* Timer/Counter3 Compare Match A */ #define TIMER3_COMPA_vect _VECTOR(26) #define SIG_OUTPUT_COMPARE3A _VECTOR(26) /* Timer/Counter3 Compare Match B */ #define TIMER3_COMPB_vect _VECTOR(27) #define SIG_OUTPUT_COMPARE3B _VECTOR(27) /* Timer/Counter3 Compare Match C */ #define TIMER3_COMPC_vect _VECTOR(28) #define SIG_OUTPUT_COMPARE3C _VECTOR(28) /* Timer/Counter3 Overflow */ #define TIMER3_OVF_vect _VECTOR(29) #define SIG_OVERFLOW3 _VECTOR(29) /* USART1, Rx Complete */ #define USART1_RX_vect _VECTOR(30) #define SIG_UART1_RECV _VECTOR(30) /* USART1, Data Register Empty */ #define USART1_UDRE_vect _VECTOR(31) #define SIG_UART1_DATA _VECTOR(31) /* USART1, Tx Complete */ #define USART1_TX_vect _VECTOR(32) #define SIG_UART1_TRANS _VECTOR(32) /* 2-wire Serial Interface */ #define TWI_vect _VECTOR(33) #define SIG_2WIRE_SERIAL _VECTOR(33) /* Store Program Memory Read */ #define SPM_READY_vect _VECTOR(34) #define SIG_SPM_READY _VECTOR(34) #define _VECTORS_SIZE 140 /* The Register Bit names are represented by their bit number (0-7). */ /* 2-wire Control Register - TWCR */ #define TWINT 7 #define TWEA 6 #define TWSTA 5 #define TWSTO 4 #define TWWC 3 #define TWEN 2 #define TWIE 0 /* 2-wire Address Register - TWAR */ #define TWA6 7 #define TWA5 6 #define TWA4 5 #define TWA3 4 #define TWA2 3 #define TWA1 2 #define TWA0 1 #define TWGCE 0 /* 2-wire Status Register - TWSR */ #define TWS7 7 #define TWS6 6 #define TWS5 5 #define TWS4 4 #define TWS3 3 #define TWPS1 1 #define TWPS0 0 /* External Memory Control Register A - XMCRA */ #define SRL2 6 #define SRL1 5 #define SRL0 4 #define SRW01 3 #define SRW00 2 #define SRW11 1 /* External Memory Control Register B - XMCRA */ #define XMBK 7 #define XMM2 2 #define XMM1 1 #define XMM0 0 /* XDIV Divide control register - XDIV */ #define XDIVEN 7 #define XDIV6 6 #define XDIV5 5 #define XDIV4 4 #define XDIV3 3 #define XDIV2 2 #define XDIV1 1 #define XDIV0 0 /* External Interrupt Control Register A - EICRA */ #define ISC31 7 #define ISC30 6 #define ISC21 5 #define ISC20 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* External Interrupt Control Register B - EICRB */ #define ISC71 7 #define ISC70 6 #define ISC61 5 #define ISC60 4 #define ISC51 3 #define ISC50 2 #define ISC41 1 #define ISC40 0 /* Store Program Memory Control Register - SPMCSR, SPMCR */ #define SPMIE 7 #define RWWSB 6 #define RWWSRE 4 #define BLBSET 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 /* External Interrupt MaSK register - EIMSK */ #define INT7 7 #define INT6 6 #define INT5 5 #define INT4 4 #define INT3 3 #define INT2 2 #define INT1 1 #define INT0 0 /* External Interrupt Flag Register - EIFR */ #define INTF7 7 #define INTF6 6 #define INTF5 5 #define INTF4 4 #define INTF3 3 #define INTF2 2 #define INTF1 1 #define INTF0 0 /* Timer/Counter Interrupt MaSK register - TIMSK */ #define OCIE2 7 #define TOIE2 6 #define TICIE1 5 #define OCIE1A 4 #define OCIE1B 3 #define TOIE1 2 #define OCIE0 1 #define TOIE0 0 /* Timer/Counter Interrupt Flag Register - TIFR */ #define OCF2 7 #define TOV2 6 #define ICF1 5 #define OCF1A 4 #define OCF1B 3 #define TOV1 2 #define OCF0 1 #define TOV0 0 /* Extended Timer Interrupt MaSK register - ETIMSK */ #define TICIE3 5 #define OCIE3A 4 #define OCIE3B 3 #define TOIE3 2 #define OCIE3C 1 #define OCIE1C 0 /* Extended Timer Interrupt Flag Register - ETIFR */ #define ICF3 5 #define OCF3A 4 #define OCF3B 3 #define TOV3 2 #define OCF3C 1 #define OCF1C 0 /* MCU Control Register - MCUCR */ #define SRE 7 #define SRW10 6 #define SE 5 #define SM1 4 #define SM0 3 #define SM2 2 #define IVSEL 1 #define IVCE 0 /* MCU Control And Status Register - MCUCSR */ #define JTD 7 #define JTRF 4 #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 /* Timer/Counter Control Register (generic) */ #define FOC 7 #define WGM0 6 #define COM1 5 #define COM0 4 #define WGM1 3 #define CS2 2 #define CS1 1 #define CS0 0 /* Timer/Counter 0 Control Register - TCCR0 */ #define FOC0 7 #define WGM00 6 #define COM01 5 #define COM00 4 #define WGM01 3 #define CS02 2 #define CS01 1 #define CS00 0 /* Timer/Counter 2 Control Register - TCCR2 */ #define FOC2 7 #define WGM20 6 #define COM21 5 #define COM20 4 #define WGM21 3 #define CS22 2 #define CS21 1 #define CS20 0 /* Timer/Counter 0 Asynchronous Control & Status Register - ASSR */ #define AS0 3 #define TCN0UB 2 #define OCR0UB 1 #define TCR0UB 0 /* Timer/Counter Control Register A (generic) */ #define COMA1 7 #define COMA0 6 #define COMB1 5 #define COMB0 4 #define COMC1 3 #define COMC0 2 #define WGMA1 1 #define WGMA0 0 /* Timer/Counter 1 Control and Status Register A - TCCR1A */ #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define COM1C1 3 #define COM1C0 2 #define WGM11 1 #define WGM10 0 /* Timer/Counter 3 Control and Status Register A - TCCR3A */ #define COM3A1 7 #define COM3A0 6 #define COM3B1 5 #define COM3B0 4 #define COM3C1 3 #define COM3C0 2 #define WGM31 1 #define WGM30 0 /* Timer/Counter Control and Status Register B (generic) */ #define ICNC 7 #define ICES 6 #define WGMB3 4 #define WGMB2 3 #define CSB2 2 #define CSB1 1 #define CSB0 0 /* Timer/Counter 1 Control and Status Register B - TCCR1B */ #define ICNC1 7 #define ICES1 6 #define WGM13 4 #define WGM12 3 #define CS12 2 #define CS11 1 #define CS10 0 /* Timer/Counter 3 Control and Status Register B - TCCR3B */ #define ICNC3 7 #define ICES3 6 #define WGM33 4 #define WGM32 3 #define CS32 2 #define CS31 1 #define CS30 0 /* Timer/Counter Control Register C (generic) */ #define FOCA 7 #define FOCB 6 #define FOCC 5 /* Timer/Counter 3 Control Register C - TCCR3C */ #define FOC3A 7 #define FOC3B 6 #define FOC3C 5 /* Timer/Counter 1 Control Register C - TCCR1C */ #define FOC1A 7 #define FOC1B 6 #define FOC1C 5 /* On-chip Debug Register - OCDR */ #define IDRD 7 #define OCDR7 7 #define OCDR6 6 #define OCDR5 5 #define OCDR4 4 #define OCDR3 3 #define OCDR2 2 #define OCDR1 1 #define OCDR0 0 /* Watchdog Timer Control Register - WDTCR */ #define WDCE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* The ADHSM bit has been removed from all documentation, as being not needed at all since the comparator has proven to be fast enough even without feeding it more power. */ /* Special Function I/O Register - SFIOR */ #define TSM 7 #define ACME 3 #define PUD 2 #define PSR0 1 #define PSR321 0 /* Port Data Register (generic) */ #define PORT7 7 #define PORT6 6 #define PORT5 5 #define PORT4 4 #define PORT3 3 #define PORT2 2 #define PORT1 1 #define PORT0 0 /* Port Data Direction Register (generic) */ #define DD7 7 #define DD6 6 #define DD5 5 #define DD4 4 #define DD3 3 #define DD2 2 #define DD1 1 #define DD0 0 /* Port Input Pins (generic) */ #define PIN7 7 #define PIN6 6 #define PIN5 5 #define PIN4 4 #define PIN3 3 #define PIN2 2 #define PIN1 1 #define PIN0 0 /* SPI Status Register - SPSR */ #define SPIF 7 #define WCOL 6 #define SPI2X 0 /* SPI Control Register - SPCR */ #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 /* USART Register C (generic) */ #define UMSEL 6 #define UPM1 5 #define UPM0 4 #define USBS 3 #define UCSZ1 2 #define UCSZ0 1 #define UCPOL 0 /* USART1 Register C - UCSR1C */ #define UMSEL1 6 #define UPM11 5 #define UPM10 4 #define USBS1 3 #define UCSZ11 2 #define UCSZ10 1 #define UCPOL1 0 /* USART0 Register C - UCSR0C */ #define UMSEL0 6 #define UPM01 5 #define UPM00 4 #define USBS0 3 #define UCSZ01 2 #define UCSZ00 1 #define UCPOL0 0 /* USART Status Register A (generic) */ #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 #define UPE 2 #define U2X 1 #define MPCM 0 /* USART1 Status Register A - UCSR1A */ #define RXC1 7 #define TXC1 6 #define UDRE1 5 #define FE1 4 #define DOR1 3 #define UPE1 2 #define U2X1 1 #define MPCM1 0 /* USART0 Status Register A - UCSR0A */ #define RXC0 7 #define TXC0 6 #define UDRE0 5 #define FE0 4 #define DOR0 3 #define UPE0 2 #define U2X0 1 #define MPCM0 0 /* USART Control Register B (generic) */ #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define UCSZ 2 #define UCSZ2 2 /* new name in datasheet (2467E-AVR-05/02) */ #define RXB8 1 #define TXB8 0 /* USART1 Control Register B - UCSR1B */ #define RXCIE1 7 #define TXCIE1 6 #define UDRIE1 5 #define RXEN1 4 #define TXEN1 3 #define UCSZ12 2 #define RXB81 1 #define TXB81 0 /* USART0 Control Register B - UCSR0B */ #define RXCIE0 7 #define TXCIE0 6 #define UDRIE0 5 #define RXEN0 4 #define TXEN0 3 #define UCSZ02 2 #define RXB80 1 #define TXB80 0 /* Analog Comparator Control and Status Register - ACSR */ #define ACD 7 #define ACBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 /* ADC Control and Status Register B - ADCSRB */ #define ADTS2 2 #define ADTS1 1 #define ADTS0 0 /* ADC Control and status Register A - ADCSRA */ #define ADEN 7 #define ADSC 6 #define ADATE 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 /* ADC Multiplexer select - ADMUX */ #define REFS1 7 #define REFS0 6 #define ADLAR 5 #define MUX4 4 #define MUX3 3 #define MUX2 2 #define MUX1 1 #define MUX0 0 /* Port A Data Register - PORTA */ #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 /* Port A Data Direction Register - DDRA */ #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 /* Port A Input Pins - PINA */ #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 /* Port B Data Register - PORTB */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* Port B Data Direction Register - DDRB */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* Port B Input Pins - PINB */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* Port C Data Register - PORTC */ #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* Port C Data Direction Register - DDRC */ #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 /* Port C Input Pins - PINC */ #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 /* Port D Data Register - PORTD */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* Port D Data Direction Register - DDRD */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* Port D Input Pins - PIND */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* Port E Data Register - PORTE */ #define PE7 7 #define PE6 6 #define PE5 5 #define PE4 4 #define PE3 3 #define PE2 2 #define PE1 1 #define PE0 0 /* Port E Data Direction Register - DDRE */ #define DDE7 7 #define DDE6 6 #define DDE5 5 #define DDE4 4 #define DDE3 3 #define DDE2 2 #define DDE1 1 #define DDE0 0 /* Port E Input Pins - PINE */ #define PINE7 7 #define PINE6 6 #define PINE5 5 #define PINE4 4 #define PINE3 3 #define PINE2 2 #define PINE1 1 #define PINE0 0 /* Port F Data Register - PORTF */ #define PF7 7 #define PF6 6 #define PF5 5 #define PF4 4 #define PF3 3 #define PF2 2 #define PF1 1 #define PF0 0 /* Port F Data Direction Register - DDRF */ #define DDF7 7 #define DDF6 6 #define DDF5 5 #define DDF4 4 #define DDF3 3 #define DDF2 2 #define DDF1 1 #define DDF0 0 /* Port F Input Pins - PINF */ #define PINF7 7 #define PINF6 6 #define PINF5 5 #define PINF4 4 #define PINF3 3 #define PINF2 2 #define PINF1 1 #define PINF0 0 /* Port G Data Register - PORTG */ #define PG4 4 #define PG3 3 #define PG2 2 #define PG1 1 #define PG0 0 /* Port G Data Direction Register - DDRG */ #define DDG4 4 #define DDG3 3 #define DDG2 2 #define DDG1 1 #define DDG0 0 /* Port G Input Pins - PING */ #define PING4 4 #define PING3 3 #define PING2 2 #define PING1 1 #define PING0 0 /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* Constants */ #define SPM_PAGESIZE 256 #define RAMEND 0x10FF /* Last On-Chip SRAM Location */ #define XRAMEND 0xFFFF #define E2END 0x07FF #define E2PAGESIZE 8 #define FLASHEND 0xFFFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_BODEN (unsigned char)~_BV(6) #define FUSE_BODLEVEL (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_CKOPT (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_WDTON (unsigned char)~_BV(0) #define FUSE_M103C (unsigned char)~_BV(1) #define EFUSE_DEFAULT (FUSE_M103C) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x96 #define SIGNATURE_2 0x02 #endif /* _AVR_IOM64_H_ */

[m64def.inc]	[iom64.h]
;*** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT **************** ;* Created: 2009-11-03 14:40 *** Source: ATmega64.xml ******** ;*********************************************************************** ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y ;* ;* Number : AVR000 ;* File Name : "m64def.inc" ;* Title : Register/Bit Definitions for the ATmega64 ;* Date : 2009-11-03 ;* Version : 2.35 ;* Support E-mail : avr@atmel.com ;* Target MCU : ATmega64 ;* ;* DESCRIPTION ;* When including this file in the assembly program file, all I/O register ;* names and I/O register bit names appearing in the data book can be used. ;* In addition, the six registers forming the three data pointers X, Y and ;* Z have been assigned names XL - ZH. Highest RAM address for Internal ;* SRAM is also defined ;* ;* The Register names are represented by their hexadecimal address. ;* ;* The Register Bit names are represented by their bit number (0-7). ;* ;* Please observe the difference in using the bit names with instructions ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" ;* (skip if bit in register set/cleared). The following example illustrates ;* this: ;* ;* in r16,PORTB ;read PORTB latch ;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) ;* out PORTB,r16 ;output to PORTB ;* ;* in r16,TIFR ;read the Timer Interrupt Flag Register ;* sbrc r16,TOV0 ;test the overflow flag (use bit#) ;* rjmp TOV0_is_set ;jump if set ;* ... ;otherwise do something else ;*********************************************************************** #ifndef _M64DEF_INC_ #define _M64DEF_INC_ #pragma partinc 0 ; * SPECIFY DEVICE *********************************************** .device ATmega64 #pragma AVRPART ADMIN PART_NAME ATmega64 .equ SIGNATURE_000 = 0x1e .equ SIGNATURE_001 = 0x96 .equ SIGNATURE_002 = 0x02 #pragma AVRPART CORE CORE_VERSION V2E ; * I/O REGISTER DEFINITIONS ************************************* ; NOTE: ; Definitions marked "MEMORY MAPPED"are extended I/O ports ; and cannot be used with IN/OUT instructions .equ UCSR1C = 0x9d ; MEMORY MAPPED .equ UDR1 = 0x9c ; MEMORY MAPPED .equ UCSR1A = 0x9b ; MEMORY MAPPED .equ UCSR1B = 0x9a ; MEMORY MAPPED .equ UBRR1H = 0x98 ; MEMORY MAPPED .equ UBRR1L = 0x99 ; MEMORY MAPPED .equ UCSR0C = 0x95 ; MEMORY MAPPED .equ UBRR0H = 0x90 ; MEMORY MAPPED .equ ADCSRB = 0x8e ; MEMORY MAPPED .equ TCCR3C = 0x8c ; MEMORY MAPPED .equ TCCR3A = 0x8b ; MEMORY MAPPED .equ TCCR3B = 0x8a ; MEMORY MAPPED .equ TCNT3L = 0x88 ; MEMORY MAPPED .equ TCNT3H = 0x89 ; MEMORY MAPPED .equ OCR3AL = 0x86 ; MEMORY MAPPED .equ OCR3AH = 0x87 ; MEMORY MAPPED .equ OCR3BL = 0x84 ; MEMORY MAPPED .equ OCR3BH = 0x85 ; MEMORY MAPPED .equ OCR3CL = 0x82 ; MEMORY MAPPED .equ OCR3CH = 0x83 ; MEMORY MAPPED .equ ICR3L = 0x80 ; MEMORY MAPPED .equ ICR3H = 0x81 ; MEMORY MAPPED .equ ETIMSK = 0x7d ; MEMORY MAPPED .equ ETIFR = 0x7c ; MEMORY MAPPED .equ TCCR1C = 0x7a ; MEMORY MAPPED .equ OCR1CL = 0x78 ; MEMORY MAPPED .equ OCR1CH = 0x79 ; MEMORY MAPPED .equ TWCR = 0x74 ; MEMORY MAPPED .equ TWDR = 0x73 ; MEMORY MAPPED .equ TWAR = 0x72 ; MEMORY MAPPED .equ TWSR = 0x71 ; MEMORY MAPPED .equ TWBR = 0x70 ; MEMORY MAPPED .equ OSCCAL = 0x6f ; MEMORY MAPPED .equ XMCRA = 0x6d ; MEMORY MAPPED .equ XMCRB = 0x6c ; MEMORY MAPPED .equ EICRA = 0x6a ; MEMORY MAPPED .equ SPMCSR = 0x68 ; MEMORY MAPPED .equ PORTG = 0x65 ; MEMORY MAPPED .equ DDRG = 0x64 ; MEMORY MAPPED .equ PING = 0x63 ; MEMORY MAPPED .equ PORTF = 0x62 ; MEMORY MAPPED .equ DDRF = 0x61 ; MEMORY MAPPED .equ SREG = 0x3f .equ SPL = 0x3d .equ SPH = 0x3e .equ XDIV = 0x3c .equ EICRB = 0x3a .equ EIMSK = 0x39 .equ EIFR = 0x38 .equ TIMSK = 0x37 .equ TIFR = 0x36 .equ MCUCR = 0x35 .equ MCUCSR = 0x34 .equ TCCR0 = 0x33 .equ TCNT0 = 0x32 .equ OCR0 = 0x31 .equ ASSR = 0x30 .equ TCCR1A = 0x2f .equ TCCR1B = 0x2e .equ TCNT1L = 0x2c .equ TCNT1H = 0x2d .equ OCR1AL = 0x2a .equ OCR1AH = 0x2b .equ OCR1BL = 0x28 .equ OCR1BH = 0x29 .equ ICR1L = 0x26 .equ ICR1H = 0x27 .equ TCCR2 = 0x25 .equ TCNT2 = 0x24 .equ OCR2 = 0x23 .equ OCDR = 0x22 .equ WDTCR = 0x21 .equ SFIOR = 0x20 .equ EEARL = 0x1e .equ EEARH = 0x1f .equ EEDR = 0x1d .equ EECR = 0x1c .equ PORTA = 0x1b .equ DDRA = 0x1a .equ PINA = 0x19 .equ PORTB = 0x18 .equ DDRB = 0x17 .equ PINB = 0x16 .equ PORTC = 0x15 .equ DDRC = 0x14 .equ PINC = 0x13 .equ PORTD = 0x12 .equ DDRD = 0x11 .equ PIND = 0x10 .equ SPDR = 0x0f .equ SPSR = 0x0e .equ SPCR = 0x0d .equ UDR0 = 0x0c .equ UCSR0A = 0x0b .equ UCSR0B = 0x0a .equ UBRR0L = 0x09 .equ ACSR = 0x08 .equ ADMUX = 0x07 .equ ADCSRA = 0x06 .equ ADCH = 0x05 .equ ADCL = 0x04 .equ PORTE = 0x03 .equ DDRE = 0x02 .equ PINE = 0x01 .equ PINF = 0x00 ; * BIT DEFINITIONS ********************************************** ; * ANALOG_COMPARATOR ******** ; SFIOR - Special Function IO Register .equ ACME = 3 ; Analog Comparator Multiplexer Enable ; ACSR - Analog Comparator Control And Status Register .equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 .equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 .equ ACIC = 2 ; Analog Comparator Input Capture Enable .equ ACIE = 3 ; Analog Comparator Interrupt Enable .equ ACI = 4 ; Analog Comparator Interrupt Flag .equ ACO = 5 ; Analog Compare Output .equ ACBG = 6 ; Analog Comparator Bandgap Select .equ ACD = 7 ; Analog Comparator Disable ; * AD_CONVERTER ************* ; ADMUX - The ADC multiplexer Selection Register .equ MUX0 = 0 ; Analog Channel and Gain Selection Bits .equ MUX1 = 1 ; Analog Channel and Gain Selection Bits .equ MUX2 = 2 ; Analog Channel and Gain Selection Bits .equ MUX3 = 3 ; Analog Channel and Gain Selection Bits .equ MUX4 = 4 ; Analog Channel and Gain Selection Bits .equ ADLAR = 5 ; Left Adjust Result .equ REFS0 = 6 ; Reference Selection Bit 0 .equ REFS1 = 7 ; Reference Selection Bit 1 ; ADCSRA - The ADC Control and Status register A .equ ADCSR = ADCSRA ; For compatibility .equ ADPS0 = 0 ; ADC Prescaler Select Bits .equ ADPS1 = 1 ; ADC Prescaler Select Bits .equ ADPS2 = 2 ; ADC Prescaler Select Bits .equ ADIE = 3 ; ADC Interrupt Enable .equ ADIF = 4 ; ADC Interrupt Flag .equ ADATE = 5 ; ADC Auto Trigger Enable .equ ADFR = ADATE ; For compatibility .equ ADSC = 6 ; ADC Start Conversion .equ ADEN = 7 ; ADC Enable ; ADCH - ADC Data Register High Byte .equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 .equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 .equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 .equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 .equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 .equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 .equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 .equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 ; ADCL - ADC Data Register Low Byte .equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 .equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 .equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 .equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 .equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 .equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 .equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 .equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 ; ADCSRB - The ADC Control and Status register B .equ ADTS0 = 0 ; ADC Auto Trigger Source bit 0 .equ ADTS1 = 1 ; ADC Auto Trigger Source bit 1 .equ ADTS2 = 2 ; ADC Auto Trigger Source bit 2 ; * SPI ********************** ; SPDR - SPI Data Register .equ SPDR0 = 0 ; SPI Data Register bit 0 .equ SPDR1 = 1 ; SPI Data Register bit 1 .equ SPDR2 = 2 ; SPI Data Register bit 2 .equ SPDR3 = 3 ; SPI Data Register bit 3 .equ SPDR4 = 4 ; SPI Data Register bit 4 .equ SPDR5 = 5 ; SPI Data Register bit 5 .equ SPDR6 = 6 ; SPI Data Register bit 6 .equ SPDR7 = 7 ; SPI Data Register bit 7 ; SPSR - SPI Status Register .equ SPI2X = 0 ; Double SPI Speed Bit .equ WCOL = 6 ; Write Collision Flag .equ SPIF = 7 ; SPI Interrupt Flag ; SPCR - SPI Control Register .equ SPR0 = 0 ; SPI Clock Rate Select 0 .equ SPR1 = 1 ; SPI Clock Rate Select 1 .equ CPHA = 2 ; Clock Phase .equ CPOL = 3 ; Clock polarity .equ MSTR = 4 ; Master/Slave Select .equ DORD = 5 ; Data Order .equ SPE = 6 ; SPI Enable .equ SPIE = 7 ; SPI Interrupt Enable ; * TWI ********************** ; TWBR - TWI Bit Rate register .equ I2BR = TWBR ; For compatibility .equ TWBR0 = 0 ; .equ TWBR1 = 1 ; .equ TWBR2 = 2 ; .equ TWBR3 = 3 ; .equ TWBR4 = 4 ; .equ TWBR5 = 5 ; .equ TWBR6 = 6 ; .equ TWBR7 = 7 ; ; TWCR - TWI Control Register .equ I2CR = TWCR ; For compatibility .equ TWIE = 0 ; TWI Interrupt Enable .equ I2IE = TWIE ; For compatibility .equ TWEN = 2 ; TWI Enable Bit .equ I2EN = TWEN ; For compatibility .equ ENI2C = TWEN ; For compatibility .equ TWWC = 3 ; TWI Write Collition Flag .equ I2WC = TWWC ; For compatibility .equ TWSTO = 4 ; TWI Stop Condition Bit .equ I2STO = TWSTO ; For compatibility .equ TWSTA = 5 ; TWI Start Condition Bit .equ I2STA = TWSTA ; For compatibility .equ TWEA = 6 ; TWI Enable Acknowledge Bit .equ I2EA = TWEA ; For compatibility .equ TWINT = 7 ; TWI Interrupt Flag .equ I2INT = TWINT ; For compatibility ; TWSR - TWI Status Register .equ I2SR = TWSR ; For compatibility .equ TWPS0 = 0 ; TWI Prescaler .equ TWS0 = TWPS0 ; For compatibility .equ I2GCE = TWPS0 ; For compatibility .equ TWPS1 = 1 ; TWI Prescaler .equ TWS1 = TWPS1 ; For compatibility .equ TWS3 = 3 ; TWI Status .equ I2S3 = TWS3 ; For compatibility .equ TWS4 = 4 ; TWI Status .equ I2S4 = TWS4 ; For compatibility .equ TWS5 = 5 ; TWI Status .equ I2S5 = TWS5 ; For compatibility .equ TWS6 = 6 ; TWI Status .equ I2S6 = TWS6 ; For compatibility .equ TWS7 = 7 ; TWI Status .equ I2S7 = TWS7 ; For compatibility ; TWDR - TWI Data register .equ I2DR = TWDR ; For compatibility .equ TWD0 = 0 ; TWI Data Register Bit 0 .equ TWD1 = 1 ; TWI Data Register Bit 1 .equ TWD2 = 2 ; TWI Data Register Bit 2 .equ TWD3 = 3 ; TWI Data Register Bit 3 .equ TWD4 = 4 ; TWI Data Register Bit 4 .equ TWD5 = 5 ; TWI Data Register Bit 5 .equ TWD6 = 6 ; TWI Data Register Bit 6 .equ TWD7 = 7 ; TWI Data Register Bit 7 ; TWAR - TWI (Slave) Address register .equ I2AR = TWAR ; For compatibility .equ TWGCE = 0 ; TWI General Call Recognition Enable Bit .equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 .equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 .equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 .equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 .equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 .equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 .equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 ; * USART0 ******************* ; UDR0 - USART I/O Data Register .equ UDR00 = 0 ; USART I/O Data Register bit 0 .equ UDR01 = 1 ; USART I/O Data Register bit 1 .equ UDR02 = 2 ; USART I/O Data Register bit 2 .equ UDR03 = 3 ; USART I/O Data Register bit 3 .equ UDR04 = 4 ; USART I/O Data Register bit 4 .equ UDR05 = 5 ; USART I/O Data Register bit 5 .equ UDR06 = 6 ; USART I/O Data Register bit 6 .equ UDR07 = 7 ; USART I/O Data Register bit 7 ; UCSR0A - USART Control and Status Register A .equ MPCM0 = 0 ; Multi-processor Communication Mode .equ U2X0 = 1 ; Double the USART transmission speed .equ UPE0 = 2 ; Parity Error .equ DOR0 = 3 ; Data overRun .equ FE0 = 4 ; Framing Error .equ UDRE0 = 5 ; USART Data Register Empty .equ TXC0 = 6 ; USART Transmitt Complete .equ RXC0 = 7 ; USART Receive Complete ; UCSR0B - USART Control and Status Register B .equ TXB80 = 0 ; Transmit Data Bit 8 .equ RXB80 = 1 ; Receive Data Bit 8 .equ UCSZ02 = 2 ; Character Size .equ UCSZ2 = UCSZ02 ; For compatibility .equ TXEN0 = 3 ; Transmitter Enable .equ RXEN0 = 4 ; Receiver Enable .equ UDRIE0 = 5 ; USART Data register Empty Interrupt Enable .equ TXCIE0 = 6 ; TX Complete Interrupt Enable .equ RXCIE0 = 7 ; RX Complete Interrupt Enable ; UCSR0C - USART Control and Status Register C .equ UCPOL0 = 0 ; Clock Polarity .equ UCSZ00 = 1 ; Character Size .equ UCSZ01 = 2 ; Character Size .equ USBS0 = 3 ; Stop Bit Select .equ UPM00 = 4 ; Parity Mode Bit 0 .equ UPM01 = 5 ; Parity Mode Bit 1 .equ UMSEL0 = 6 ; USART Mode Select ; UBRR0H - USART Baud Rate Register Hight Byte .equ UBRR8 = 0 ; USART Baud Rate Register bit 8 .equ UBRR9 = 1 ; USART Baud Rate Register bit 9 .equ UBRR10 = 2 ; USART Baud Rate Register bit 10 .equ UBRR11 = 3 ; USART Baud Rate Register bit 11 ; UBRR0L - USART Baud Rate Register Low Byte .equ UBRR0 = 0 ; USART Baud Rate Register bit 0 .equ UBRR1 = 1 ; USART Baud Rate Register bit 1 .equ UBRR2 = 2 ; USART Baud Rate Register bit 2 .equ UBRR3 = 3 ; USART Baud Rate Register bit 3 .equ UBRR4 = 4 ; USART Baud Rate Register bit 4 .equ UBRR5 = 5 ; USART Baud Rate Register bit 5 .equ UBRR6 = 6 ; USART Baud Rate Register bit 6 .equ UBRR7 = 7 ; USART Baud Rate Register bit 7 ; * USART1 ******************* ; UDR1 - USART I/O Data Register .equ UDR10 = 0 ; USART I/O Data Register bit 0 .equ UDR11 = 1 ; USART I/O Data Register bit 1 .equ UDR12 = 2 ; USART I/O Data Register bit 2 .equ UDR13 = 3 ; USART I/O Data Register bit 3 .equ UDR14 = 4 ; USART I/O Data Register bit 4 .equ UDR15 = 5 ; USART I/O Data Register bit 5 .equ UDR16 = 6 ; USART I/O Data Register bit 6 .equ UDR17 = 7 ; USART I/O Data Register bit 7 ; UCSR1A - USART Control and Status Register A .equ MPCM1 = 0 ; Multi-processor Communication Mode .equ U2X1 = 1 ; Double the USART transmission speed .equ UPE1 = 2 ; Parity Error .equ DOR1 = 3 ; Data overRun .equ FE1 = 4 ; Framing Error .equ UDRE1 = 5 ; USART Data Register Empty .equ TXC1 = 6 ; USART Transmitt Complete .equ RXC1 = 7 ; USART Receive Complete ; UCSR1B - USART Control and Status Register B .equ TXB81 = 0 ; Transmit Data Bit 8 .equ RXB81 = 1 ; Receive Data Bit 8 .equ UCSZ12 = 2 ; Character Size .equ TXEN1 = 3 ; Transmitter Enable .equ RXEN1 = 4 ; Receiver Enable .equ UDRIE1 = 5 ; USART Data register Empty Interrupt Enable .equ TXCIE1 = 6 ; TX Complete Interrupt Enable .equ RXCIE1 = 7 ; RX Complete Interrupt Enable ; UCSR1C - USART Control and Status Register C .equ UCPOL1 = 0 ; Clock Polarity .equ UCSZ10 = 1 ; Character Size .equ UCSZ11 = 2 ; Character Size .equ USBS1 = 3 ; Stop Bit Select .equ UPM10 = 4 ; Parity Mode Bit 0 .equ UPM11 = 5 ; Parity Mode Bit 1 .equ UMSEL1 = 6 ; USART Mode Select ; UBRR1H - USART Baud Rate Register Hight Byte ;.equ UBRR8 = 0 ; USART Baud Rate Register bit 8 ;.equ UBRR9 = 1 ; USART Baud Rate Register bit 9 ;.equ UBRR10 = 2 ; USART Baud Rate Register bit 10 ;.equ UBRR11 = 3 ; USART Baud Rate Register bit 11 ; UBRR1L - USART Baud Rate Register Low Byte ;.equ UBRR0 = 0 ; USART Baud Rate Register bit 0 ;.equ UBRR1 = 1 ; USART Baud Rate Register bit 1 ;.equ UBRR2 = 2 ; USART Baud Rate Register bit 2 ;.equ UBRR3 = 3 ; USART Baud Rate Register bit 3 ;.equ UBRR4 = 4 ; USART Baud Rate Register bit 4 ;.equ UBRR5 = 5 ; USART Baud Rate Register bit 5 ;.equ UBRR6 = 6 ; USART Baud Rate Register bit 6 ;.equ UBRR7 = 7 ; USART Baud Rate Register bit 7 ; * CPU ********************** ; SREG - Status Register .equ SREG_C = 0 ; Carry Flag .equ SREG_Z = 1 ; Zero Flag .equ SREG_N = 2 ; Negative Flag .equ SREG_V = 3 ; Two's Complement Overflow Flag .equ SREG_S = 4 ; Sign Bit .equ SREG_H = 5 ; Half Carry Flag .equ SREG_T = 6 ; Bit Copy Storage .equ SREG_I = 7 ; Global Interrupt Enable ; MCUCR - MCU Control Register .equ IVCE = 0 ; Interrupt Vector Change Enable .equ IVSEL = 1 ; Interrupt Vector Select .equ SM2 = 2 ; Sleep Mode Select .equ SM0 = 3 ; Sleep Mode Select .equ SM1 = 4 ; Sleep Mode Select .equ SE = 5 ; Sleep Enable .equ SRW10 = 6 ; External SRAM Wait State Select .equ SRE = 7 ; External SRAM Enable ; XMCRA - External Memory Control Register A .equ SRW11 = 1 ; Wait state select bit upper page .equ SRW00 = 2 ; Wait state select bit lower page .equ SRW01 = 3 ; Wait state select bit lower page .equ SRL0 = 4 ; Wait state page limit .equ SRL1 = 5 ; Wait state page limit .equ SRL2 = 6 ; Wait state page limit ; XMCRB - External Memory Control Register B .equ XMM0 = 0 ; External Memory High Mask .equ XMM1 = 1 ; External Memory High Mask .equ XMM2 = 2 ; External Memory High Mask .equ XMBK = 7 ; External Memory Bus Keeper Enable ; OSCCAL - Oscillator Calibration Value .equ CAL0 = 0 ; Oscillator Calibration Value .equ CAL1 = 1 ; Oscillator Calibration Value .equ CAL2 = 2 ; Oscillator Calibration Value .equ CAL3 = 3 ; Oscillator Calibration Value .equ CAL4 = 4 ; Oscillator Calibration Value .equ CAL5 = 5 ; Oscillator Calibration Value .equ CAL6 = 6 ; Oscillator Calibration Value .equ CAL7 = 7 ; Oscillator Calibration Value ; XDIV - XTAL Divide Control Register .equ XDIV0 = 0 ; XTAl Divide Select Bit 0 .equ XDIV1 = 1 ; XTAl Divide Select Bit 1 .equ XDIV2 = 2 ; XTAl Divide Select Bit 2 .equ XDIV3 = 3 ; XTAl Divide Select Bit 3 .equ XDIV4 = 4 ; XTAl Divide Select Bit 4 .equ XDIV5 = 5 ; XTAl Divide Select Bit 5 .equ XDIV6 = 6 ; XTAl Divide Select Bit 6 .equ XDIVEN = 7 ; XTAL Divide Enable ; MCUCSR - MCU Control And Status Register .equ PORF = 0 ; Power-on reset flag .equ EXTRF = 1 ; External Reset Flag .equ BORF = 2 ; Brown-out Reset Flag .equ WDRF = 3 ; Watchdog Reset Flag .equ JTRF = 4 ; JTAG Reset Flag .equ JTD = 7 ; JTAG Interface Disable ; * BOOT_LOAD **************** ; SPMCSR - Store Program Memory Control Register .equ SPMCR = SPMCSR ; For compatibility .equ SPMEN = 0 ; Store Program Memory Enable .equ PGERS = 1 ; Page Erase .equ PGWRT = 2 ; Page Write .equ BLBSET = 3 ; Boot Lock Bit Set .equ RWWSRE = 4 ; Read While Write section read enable .equ ASRE = RWWSRE ; For compatibility .equ RWWSB = 6 ; Read While Write Section Busy .equ ASB = RWWSB ; For compatibility .equ SPMIE = 7 ; SPM Interrupt Enable ; * JTAG ********************* ; OCDR - On-Chip Debug Related Register in I/O Memory .equ OCDR0 = 0 ; On-Chip Debug Register Bit 0 .equ OCDR1 = 1 ; On-Chip Debug Register Bit 1 .equ OCDR2 = 2 ; On-Chip Debug Register Bit 2 .equ OCDR3 = 3 ; On-Chip Debug Register Bit 3 .equ OCDR4 = 4 ; On-Chip Debug Register Bit 4 .equ OCDR5 = 5 ; On-Chip Debug Register Bit 5 .equ OCDR6 = 6 ; On-Chip Debug Register Bit 6 .equ OCDR7 = 7 ; On-Chip Debug Register Bit 7 .equ IDRD = OCDR7 ; For compatibility ; MCUCSR - MCU Control And Status Register ;.equ JTRF = 4 ; JTAG Reset Flag ;.equ JTD = 7 ; JTAG Interface Disable ; * MISC ********************* ; SFIOR - Special Function IO Register .equ PSR321 = 0 ; Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1 .equ PSR1 = PSR321 ; For compatibility .equ PSR2 = PSR321 ; For compatibility .equ PSR3 = PSR321 ; For compatibility .equ PSR0 = 1 ; Prescaler Reset Timer/Counter0 .equ PUD = 2 ; Pull Up Disable ;.equ ACME = 3 ; Analog Comparator Multiplexer Enable .equ TSM = 7 ; Timer/Counter Synchronization Mode ; * EXTERNAL_INTERRUPT ******* ; EICRA - External Interrupt Control Register A .equ ISC00 = 0 ; External Interrupt Sense Control Bit .equ ISC01 = 1 ; External Interrupt Sense Control Bit .equ ISC10 = 2 ; External Interrupt Sense Control Bit .equ ISC11 = 3 ; External Interrupt Sense Control Bit .equ ISC20 = 4 ; External Interrupt Sense Control Bit .equ ISC21 = 5 ; External Interrupt Sense Control Bit .equ ISC30 = 6 ; External Interrupt Sense Control Bit .equ ISC31 = 7 ; External Interrupt Sense Control Bit ; EICRB - External Interrupt Control Register B .equ ISC40 = 0 ; External Interrupt 7-4 Sense Control Bit .equ ISC41 = 1 ; External Interrupt 7-4 Sense Control Bit .equ ISC50 = 2 ; External Interrupt 7-4 Sense Control Bit .equ ISC51 = 3 ; External Interrupt 7-4 Sense Control Bit .equ ISC60 = 4 ; External Interrupt 7-4 Sense Control Bit .equ ISC61 = 5 ; External Interrupt 7-4 Sense Control Bit .equ ISC70 = 6 ; External Interrupt 7-4 Sense Control Bit .equ ISC71 = 7 ; External Interrupt 7-4 Sense Control Bit ; EIMSK - External Interrupt Mask Register .equ GICR = EIMSK ; For compatibility .equ GIMSK = EIMSK ; For compatibility .equ INT0 = 0 ; External Interrupt Request 0 Enable .equ INT1 = 1 ; External Interrupt Request 1 Enable .equ INT2 = 2 ; External Interrupt Request 2 Enable .equ INT3 = 3 ; External Interrupt Request 3 Enable .equ INT4 = 4 ; External Interrupt Request 4 Enable .equ INT5 = 5 ; External Interrupt Request 5 Enable .equ INT6 = 6 ; External Interrupt Request 6 Enable .equ INT7 = 7 ; External Interrupt Request 7 Enable ; EIFR - External Interrupt Flag Register .equ GIFR = EIFR ; For compatibility .equ INTF0 = 0 ; External Interrupt Flag 0 .equ INTF1 = 1 ; External Interrupt Flag 1 .equ INTF2 = 2 ; External Interrupt Flag 2 .equ INTF3 = 3 ; External Interrupt Flag 3 .equ INTF4 = 4 ; External Interrupt Flag 4 .equ INTF5 = 5 ; External Interrupt Flag 5 .equ INTF6 = 6 ; External Interrupt Flag 6 .equ INTF7 = 7 ; External Interrupt Flag 7 ; * EEPROM ******************* ; EEDR - EEPROM Data Register .equ EEDR0 = 0 ; EEPROM Data Register bit 0 .equ EEDR1 = 1 ; EEPROM Data Register bit 1 .equ EEDR2 = 2 ; EEPROM Data Register bit 2 .equ EEDR3 = 3 ; EEPROM Data Register bit 3 .equ EEDR4 = 4 ; EEPROM Data Register bit 4 .equ EEDR5 = 5 ; EEPROM Data Register bit 5 .equ EEDR6 = 6 ; EEPROM Data Register bit 6 .equ EEDR7 = 7 ; EEPROM Data Register bit 7 ; EECR - EEPROM Control Register .equ EERE = 0 ; EEPROM Read Enable .equ EEWE = 1 ; EEPROM Write Enable .equ EEMWE = 2 ; EEPROM Master Write Enable .equ EERIE = 3 ; EEPROM Ready Interrupt Enable ; * PORTA ******************** ; PORTA - Port A Data Register .equ PORTA0 = 0 ; Port A Data Register bit 0 .equ PA0 = 0 ; For compatibility .equ PORTA1 = 1 ; Port A Data Register bit 1 .equ PA1 = 1 ; For compatibility .equ PORTA2 = 2 ; Port A Data Register bit 2 .equ PA2 = 2 ; For compatibility .equ PORTA3 = 3 ; Port A Data Register bit 3 .equ PA3 = 3 ; For compatibility .equ PORTA4 = 4 ; Port A Data Register bit 4 .equ PA4 = 4 ; For compatibility .equ PORTA5 = 5 ; Port A Data Register bit 5 .equ PA5 = 5 ; For compatibility .equ PORTA6 = 6 ; Port A Data Register bit 6 .equ PA6 = 6 ; For compatibility .equ PORTA7 = 7 ; Port A Data Register bit 7 .equ PA7 = 7 ; For compatibility ; DDRA - Port A Data Direction Register .equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 .equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 .equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 .equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 .equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 .equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 .equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 .equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 ; PINA - Port A Input Pins .equ PINA0 = 0 ; Input Pins, Port A bit 0 .equ PINA1 = 1 ; Input Pins, Port A bit 1 .equ PINA2 = 2 ; Input Pins, Port A bit 2 .equ PINA3 = 3 ; Input Pins, Port A bit 3 .equ PINA4 = 4 ; Input Pins, Port A bit 4 .equ PINA5 = 5 ; Input Pins, Port A bit 5 .equ PINA6 = 6 ; Input Pins, Port A bit 6 .equ PINA7 = 7 ; Input Pins, Port A bit 7 ; * PORTB ******************** ; PORTB - Port B Data Register .equ PORTB0 = 0 ; Port B Data Register bit 0 .equ PB0 = 0 ; For compatibility .equ PORTB1 = 1 ; Port B Data Register bit 1 .equ PB1 = 1 ; For compatibility .equ PORTB2 = 2 ; Port B Data Register bit 2 .equ PB2 = 2 ; For compatibility .equ PORTB3 = 3 ; Port B Data Register bit 3 .equ PB3 = 3 ; For compatibility .equ PORTB4 = 4 ; Port B Data Register bit 4 .equ PB4 = 4 ; For compatibility .equ PORTB5 = 5 ; Port B Data Register bit 5 .equ PB5 = 5 ; For compatibility .equ PORTB6 = 6 ; Port B Data Register bit 6 .equ PB6 = 6 ; For compatibility .equ PORTB7 = 7 ; Port B Data Register bit 7 .equ PB7 = 7 ; For compatibility ; DDRB - Port B Data Direction Register .equ DDB0 = 0 ; Port B Data Direction Register bit 0 .equ DDB1 = 1 ; Port B Data Direction Register bit 1 .equ DDB2 = 2 ; Port B Data Direction Register bit 2 .equ DDB3 = 3 ; Port B Data Direction Register bit 3 .equ DDB4 = 4 ; Port B Data Direction Register bit 4 .equ DDB5 = 5 ; Port B Data Direction Register bit 5 .equ DDB6 = 6 ; Port B Data Direction Register bit 6 .equ DDB7 = 7 ; Port B Data Direction Register bit 7 ; PINB - Port B Input Pins .equ PINB0 = 0 ; Port B Input Pins bit 0 .equ PINB1 = 1 ; Port B Input Pins bit 1 .equ PINB2 = 2 ; Port B Input Pins bit 2 .equ PINB3 = 3 ; Port B Input Pins bit 3 .equ PINB4 = 4 ; Port B Input Pins bit 4 .equ PINB5 = 5 ; Port B Input Pins bit 5 .equ PINB6 = 6 ; Port B Input Pins bit 6 .equ PINB7 = 7 ; Port B Input Pins bit 7 ; * PORTC ******************** ; PORTC - Port C Data Register .equ PORTC0 = 0 ; Port C Data Register bit 0 .equ PC0 = 0 ; For compatibility .equ PORTC1 = 1 ; Port C Data Register bit 1 .equ PC1 = 1 ; For compatibility .equ PORTC2 = 2 ; Port C Data Register bit 2 .equ PC2 = 2 ; For compatibility .equ PORTC3 = 3 ; Port C Data Register bit 3 .equ PC3 = 3 ; For compatibility .equ PORTC4 = 4 ; Port C Data Register bit 4 .equ PC4 = 4 ; For compatibility .equ PORTC5 = 5 ; Port C Data Register bit 5 .equ PC5 = 5 ; For compatibility .equ PORTC6 = 6 ; Port C Data Register bit 6 .equ PC6 = 6 ; For compatibility .equ PORTC7 = 7 ; Port C Data Register bit 7 .equ PC7 = 7 ; For compatibility ; DDRC - Port C Data Direction Register .equ DDC0 = 0 ; Port C Data Direction Register bit 0 .equ DDC1 = 1 ; Port C Data Direction Register bit 1 .equ DDC2 = 2 ; Port C Data Direction Register bit 2 .equ DDC3 = 3 ; Port C Data Direction Register bit 3 .equ DDC4 = 4 ; Port C Data Direction Register bit 4 .equ DDC5 = 5 ; Port C Data Direction Register bit 5 .equ DDC6 = 6 ; Port C Data Direction Register bit 6 .equ DDC7 = 7 ; Port C Data Direction Register bit 7 ; PINC - Port C Input Pins .equ PINC0 = 0 ; Port C Input Pins bit 0 .equ PINC1 = 1 ; Port C Input Pins bit 1 .equ PINC2 = 2 ; Port C Input Pins bit 2 .equ PINC3 = 3 ; Port C Input Pins bit 3 .equ PINC4 = 4 ; Port C Input Pins bit 4 .equ PINC5 = 5 ; Port C Input Pins bit 5 .equ PINC6 = 6 ; Port C Input Pins bit 6 .equ PINC7 = 7 ; Port C Input Pins bit 7 ; * PORTD ******************** ; PORTD - Port D Data Register .equ PORTD0 = 0 ; Port D Data Register bit 0 .equ PD0 = 0 ; For compatibility .equ PORTD1 = 1 ; Port D Data Register bit 1 .equ PD1 = 1 ; For compatibility .equ PORTD2 = 2 ; Port D Data Register bit 2 .equ PD2 = 2 ; For compatibility .equ PORTD3 = 3 ; Port D Data Register bit 3 .equ PD3 = 3 ; For compatibility .equ PORTD4 = 4 ; Port D Data Register bit 4 .equ PD4 = 4 ; For compatibility .equ PORTD5 = 5 ; Port D Data Register bit 5 .equ PD5 = 5 ; For compatibility .equ PORTD6 = 6 ; Port D Data Register bit 6 .equ PD6 = 6 ; For compatibility .equ PORTD7 = 7 ; Port D Data Register bit 7 .equ PD7 = 7 ; For compatibility ; DDRD - Port D Data Direction Register .equ DDD0 = 0 ; Port D Data Direction Register bit 0 .equ DDD1 = 1 ; Port D Data Direction Register bit 1 .equ DDD2 = 2 ; Port D Data Direction Register bit 2 .equ DDD3 = 3 ; Port D Data Direction Register bit 3 .equ DDD4 = 4 ; Port D Data Direction Register bit 4 .equ DDD5 = 5 ; Port D Data Direction Register bit 5 .equ DDD6 = 6 ; Port D Data Direction Register bit 6 .equ DDD7 = 7 ; Port D Data Direction Register bit 7 ; PIND - Port D Input Pins .equ PIND0 = 0 ; Port D Input Pins bit 0 .equ PIND1 = 1 ; Port D Input Pins bit 1 .equ PIND2 = 2 ; Port D Input Pins bit 2 .equ PIND3 = 3 ; Port D Input Pins bit 3 .equ PIND4 = 4 ; Port D Input Pins bit 4 .equ PIND5 = 5 ; Port D Input Pins bit 5 .equ PIND6 = 6 ; Port D Input Pins bit 6 .equ PIND7 = 7 ; Port D Input Pins bit 7 ; * PORTE ******************** ; PORTE - Data Register, Port E .equ PORTE0 = 0 ; .equ PE0 = 0 ; For compatibility .equ PORTE1 = 1 ; .equ PE1 = 1 ; For compatibility .equ PORTE2 = 2 ; .equ PE2 = 2 ; For compatibility .equ PORTE3 = 3 ; .equ PE3 = 3 ; For compatibility .equ PORTE4 = 4 ; .equ PE4 = 4 ; For compatibility .equ PORTE5 = 5 ; .equ PE5 = 5 ; For compatibility .equ PORTE6 = 6 ; .equ PE6 = 6 ; For compatibility .equ PORTE7 = 7 ; .equ PE7 = 7 ; For compatibility ; DDRE - Data Direction Register, Port E .equ DDE0 = 0 ; .equ DDE1 = 1 ; .equ DDE2 = 2 ; .equ DDE3 = 3 ; .equ DDE4 = 4 ; .equ DDE5 = 5 ; .equ DDE6 = 6 ; .equ DDE7 = 7 ; ; PINE - Input Pins, Port E .equ PINE0 = 0 ; .equ PINE1 = 1 ; .equ PINE2 = 2 ; .equ PINE3 = 3 ; .equ PINE4 = 4 ; .equ PINE5 = 5 ; .equ PINE6 = 6 ; .equ PINE7 = 7 ; ; * PORTF ******************** ; PORTF - Data Register, Port F .equ PORTF0 = 0 ; .equ PF0 = 0 ; For compatibility .equ PORTF1 = 1 ; .equ PF1 = 1 ; For compatibility .equ PORTF2 = 2 ; .equ PF2 = 2 ; For compatibility .equ PORTF3 = 3 ; .equ PF3 = 3 ; For compatibility .equ PORTF4 = 4 ; .equ PF4 = 4 ; For compatibility .equ PORTF5 = 5 ; .equ PF5 = 5 ; For compatibility .equ PORTF6 = 6 ; .equ PF6 = 6 ; For compatibility .equ PORTF7 = 7 ; .equ PF7 = 7 ; For compatibility ; DDRF - Data Direction Register, Port F .equ DDF0 = 0 ; .equ DDF1 = 1 ; .equ DDF2 = 2 ; .equ DDF3 = 3 ; .equ DDF4 = 4 ; .equ DDF5 = 5 ; .equ DDF6 = 6 ; .equ DDF7 = 7 ; ; PINF - Input Pins, Port F .equ PINF0 = 0 ; .equ PINF1 = 1 ; .equ PINF2 = 2 ; .equ PINF3 = 3 ; .equ PINF4 = 4 ; .equ PINF5 = 5 ; .equ PINF6 = 6 ; .equ PINF7 = 7 ; ; * PORTG ******************** ; PORTG - Data Register, Port G .equ PORTG0 = 0 ; .equ PG0 = 0 ; For compatibility .equ PORTG1 = 1 ; .equ PG1 = 1 ; For compatibility .equ PORTG2 = 2 ; .equ PG2 = 2 ; For compatibility .equ PORTG3 = 3 ; .equ PG3 = 3 ; For compatibility .equ PORTG4 = 4 ; .equ PG4 = 4 ; For compatibility ; DDRG - Data Direction Register, Port G .equ DDG0 = 0 ; .equ DDG1 = 1 ; .equ DDG2 = 2 ; .equ DDG3 = 3 ; .equ DDG4 = 4 ; ; PING - Input Pins, Port G .equ PING0 = 0 ; .equ PING1 = 1 ; .equ PING2 = 2 ; .equ PING3 = 3 ; .equ PING4 = 4 ; ; * TIMER_COUNTER_0 ********** ; TCCR0 - Timer/Counter Control Register .equ CS00 = 0 ; Clock Select 0 .equ CS01 = 1 ; Clock Select 1 .equ CS02 = 2 ; Clock Select 2 .equ WGM01 = 3 ; Waveform Generation Mode 1 .equ CTC0 = WGM01 ; For compatibility .equ COM00 = 4 ; Compare match Output Mode 0 .equ COM01 = 5 ; Compare Match Output Mode 1 .equ WGM00 = 6 ; Waveform Generation Mode 0 .equ PWM0 = WGM00 ; For compatibility .equ FOC0 = 7 ; Force Output Compare ; TCNT0 - Timer/Counter Register .equ TCNT0_0 = 0 ; .equ TCNT0_1 = 1 ; .equ TCNT0_2 = 2 ; .equ TCNT0_3 = 3 ; .equ TCNT0_4 = 4 ; .equ TCNT0_5 = 5 ; .equ TCNT0_6 = 6 ; .equ TCNT0_7 = 7 ; ; OCR0 - Output Compare Register .equ OCR0_0 = 0 ; .equ OCR0_1 = 1 ; .equ OCR0_2 = 2 ; .equ OCR0_3 = 3 ; .equ OCR0_4 = 4 ; .equ OCR0_5 = 5 ; .equ OCR0_6 = 6 ; .equ OCR0_7 = 7 ; ; ASSR - Asynchronus Status Register .equ TCR0UB = 0 ; Timer/Counter Control Register 0 Update Busy .equ OCR0UB = 1 ; Output Compare register 0 Busy .equ TCN0UB = 2 ; Timer/Counter0 Update Busy .equ AS0 = 3 ; Asynchronus Timer/Counter 0 ; TIMSK - Timer/Counter Interrupt Mask Register .equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable .equ OCIE0 = 1 ; Timer/Counter0 Output Compare Match Interrupt register ; TIFR - Timer/Counter Interrupt Flag register .equ TOV0 = 0 ; Timer/Counter0 Overflow Flag .equ OCF0 = 1 ; Output Compare Flag 0 ; SFIOR - Special Function IO Register ;.equ PSR0 = 1 ; Prescaler Reset Timer/Counter0 ;.equ TSM = 7 ; Timer/Counter Synchronization Mode ; * TIMER_COUNTER_1 ********** ; TIMSK - Timer/Counter Interrupt Mask Register .equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable .equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable .equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable .equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable ; ETIMSK - Extended Timer/Counter Interrupt Mask Register .equ OCIE1C = 0 ; Timer/Counter 1, Output Compare Match C Interrupt Enable ; TIFR - Timer/Counter Interrupt Flag register .equ TOV1 = 2 ; Timer/Counter1 Overflow Flag .equ OCF1B = 3 ; Output Compare Flag 1B .equ OCF1A = 4 ; Output Compare Flag 1A .equ ICF1 = 5 ; Input Capture Flag 1 ; ETIFR - Extended Timer/Counter Interrupt Flag register .equ OCF1C = 0 ; Timer/Counter 1, Output Compare C Match Flag ; SFIOR - Special Function IO Register ;.equ PSR321 = 0 ; Prescaler Reset, T/C3, T/C2, T/C1 ;.equ TSM = 7 ; Timer/Counter Synchronization Mode ; TCCR1A - Timer/Counter1 Control Register A .equ WGM10 = 0 ; Waveform Generation Mode Bit 0 .equ PWM10 = WGM10 ; For compatibility .equ WGM11 = 1 ; Waveform Generation Mode Bit 1 .equ PWM11 = WGM11 ; For compatibility .equ COM1C0 = 2 ; Compare Output Mode 1C, bit 0 .equ COM1C1 = 3 ; Compare Output Mode 1C, bit 1 .equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 .equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 .equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0 .equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 ; TCCR1B - Timer/Counter1 Control Register B .equ CS10 = 0 ; Clock Select bit 0 .equ CS11 = 1 ; Clock Select 1 bit 1 .equ CS12 = 2 ; Clock Select1 bit 2 .equ WGM12 = 3 ; Waveform Generation Mode .equ CTC10 = WGM12 ; For compatibility .equ WGM13 = 4 ; Waveform Generation Mode .equ CTC11 = WGM13 ; For compatibility .equ ICES1 = 6 ; Input Capture 1 Edge Select .equ ICNC1 = 7 ; Input Capture 1 Noise Canceler ; TCCR1C - Timer/Counter1 Control Register C .equ FOC1C = 5 ; Force Output Compare for channel C .equ FOC1B = 6 ; Force Output Compare for channel B .equ FOC1A = 7 ; Force Output Compare for channel A ; * TIMER_COUNTER_2 ********** ; TCCR2 - Timer/Counter Control Register .equ CS20 = 0 ; Clock Select .equ CS21 = 1 ; Clock Select .equ CS22 = 2 ; Clock Select .equ WGM21 = 3 ; Waveform Generation Mode .equ CTC2 = WGM21 ; For compatibility .equ COM20 = 4 ; Compare Match Output Mode .equ COM21 = 5 ; Compare Match Output Mode .equ WGM20 = 6 ; Wafeform Generation Mode .equ PWM2 = WGM20 ; For compatibility .equ FOC2 = 7 ; Force Output Compare ; TCNT2 - Timer/Counter Register .equ TCNT2_0 = 0 ; Timer/Counter Register Bit 0 .equ TCNT2_1 = 1 ; Timer/Counter Register Bit 1 .equ TCNT2_2 = 2 ; Timer/Counter Register Bit 2 .equ TCNT2_3 = 3 ; Timer/Counter Register Bit 3 .equ TCNT2_4 = 4 ; Timer/Counter Register Bit 4 .equ TCNT2_5 = 5 ; Timer/Counter Register Bit 5 .equ TCNT2_6 = 6 ; Timer/Counter Register Bit 6 .equ TCNT2_7 = 7 ; Timer/Counter Register Bit 7 ; OCR2 - Output Compare Register .equ OCR2_0 = 0 ; Output Compare Register Bit 0 .equ OCR2_1 = 1 ; Output Compare Register Bit 1 .equ OCR2_2 = 2 ; Output Compare Register Bit 2 .equ OCR2_3 = 3 ; Output Compare Register Bit 3 .equ OCR2_4 = 4 ; Output Compare Register Bit 4 .equ OCR2_5 = 5 ; Output Compare Register Bit 5 .equ OCR2_6 = 6 ; Output Compare Register Bit 6 .equ OCR2_7 = 7 ; Output Compare Register Bit 7 ; TIMSK - .equ TOIE2 = 6 ; .equ OCIE2 = 7 ; ; TIFR - Timer/Counter Interrupt Flag Register .equ TOV2 = 6 ; Timer/Counter2 Overflow Flag .equ OCF2 = 7 ; Output Compare Flag 2 ; * TIMER_COUNTER_3 ********** ; ETIMSK - Extended Timer/Counter Interrupt Mask Register .equ OCIE3C = 1 ; Timer/Counter3, Output Compare Match Interrupt Enable .equ TOIE3 = 2 ; Timer/Counter3 Overflow Interrupt Enable .equ OCIE3B = 3 ; Timer/Counter3 Output CompareB Match Interrupt Enable .equ OCIE3A = 4 ; Timer/Counter3 Output CompareA Match Interrupt Enable .equ TICIE3 = 5 ; Timer/Counter3 Input Capture Interrupt Enable ; ETIFR - Extended Timer/Counter Interrupt Flag register .equ OCF3C = 1 ; Timer/Counter3 Output Compare C Match Flag .equ TOV3 = 2 ; Timer/Counter3 Overflow Flag .equ OCF3B = 3 ; Output Compare Flag 1B .equ OCF3A = 4 ; Output Compare Flag 1A .equ ICF3 = 5 ; Input Capture Flag 1 ; SFIOR - Special Function IO Register ;.equ PSR321 = 0 ; Prescaler Reset, T/C3, T/C2, T/C1 ;.equ PSR1 = PSR321 ; For compatibility ;.equ PSR2 = PSR321 ; For compatibility ;.equ TSM = 7 ; Timer/Counter Synchronization Mode ; TCCR3A - Timer/Counter3 Control Register A .equ WGM30 = 0 ; Waveform Generation Mode Bit 0 .equ PWM30 = WGM30 ; For compatibility .equ WGM31 = 1 ; Waveform Generation Mode Bit 1 .equ PWM31 = WGM31 ; For compatibility .equ COM3C0 = 2 ; Compare Output Mode 3C, bit 0 .equ COM3C1 = 3 ; Compare Output Mode 3C, bit 1 .equ COM3B0 = 4 ; Compare Output Mode 3B, bit 0 .equ COM3B1 = 5 ; Compare Output Mode 3B, bit 1 .equ COM3A0 = 6 ; Comparet Ouput Mode 3A, bit 0 .equ COM3A1 = 7 ; Compare Output Mode 3A, bit 1 ; TCCR3B - Timer/Counter3 Control Register B .equ CS30 = 0 ; Clock Select 3 bit 0 .equ CS31 = 1 ; Clock Select 3 bit 1 .equ CS32 = 2 ; Clock Select3 bit 2 .equ WGM32 = 3 ; Waveform Generation Mode .equ CTC30 = WGM32 ; For compatibility .equ WGM33 = 4 ; Waveform Generation Mode .equ CTC31 = WGM33 ; For compatibility .equ ICES3 = 6 ; Input Capture 3 Edge Select .equ ICNC3 = 7 ; Input Capture 3 Noise Canceler ; TCCR3C - Timer/Counter3 Control Register C .equ FOC3C = 5 ; Force Output Compare for channel C .equ FOC3B = 6 ; Force Output Compare for channel B .equ FOC3A = 7 ; Force Output Compare for channel A ; TCNT3L - Timer/Counter3 Low Byte .equ TCN3L0 = 0 ; Timer/Counter 3 bit 0 .equ TCN3L1 = 1 ; Timer/Counter 3 bit 1 .equ TCN3L2 = 2 ; Timer/Counter 3 bit 2 .equ TCN3L3 = 3 ; Timer/Counter 3 bit 3 .equ TCN3L4 = 4 ; Timer/Counter 3 bit 4 .equ TCN3L5 = 5 ; Timer/Counter 3 bit 5 .equ TCN3L6 = 6 ; Timer/Counter 3 bit 6 .equ TCN3L7 = 7 ; Timer/Counter 3 bit 7 ; * WATCHDOG ***************** ; WDTCR - Watchdog Timer Control Register .equ WDTCSR = WDTCR ; For compatibility .equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 .equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 .equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 .equ WDE = 3 ; Watch Dog Enable .equ WDCE = 4 ; Watchdog Change Enable .equ WDTOE = WDCE ; For compatibility ; * LOCKSBITS **************************************************** .equ LB1 = 0 ; Lock bit .equ LB2 = 1 ; Lock bit .equ BLB01 = 2 ; Boot Lock bit .equ BLB02 = 3 ; Boot Lock bit .equ BLB11 = 4 ; Boot lock bit .equ BLB12 = 5 ; Boot lock bit ; * FUSES ******************************************************** ; LOW fuse bits .equ CKSEL0 = 0 ; Select Clock Source .equ CKSEL1 = 1 ; Select Clock Source .equ CKSEL2 = 2 ; Select Clock Source .equ CKSEL3 = 3 ; Select Clock Source .equ SUT0 = 4 ; Select start-up time .equ SUT1 = 5 ; Select start-up time .equ BODEN = 6 ; Brown out detector enable .equ BODLEVEL = 7 ; Brown out detector trigger level ; HIGH fuse bits .equ BOOTRST = 0 ; Select Reset Vector .equ BOOTSZ0 = 1 ; Select Boot Size .equ BOOTSZ1 = 2 ; Select Boot Size .equ EESAVE = 3 ; EEPROM memory is preserved through chip erase .equ CKOPT = 4 ; Oscillator Options .equ SPIEN = 5 ; Enable Serial programming and Data Downloading .equ JTAGEN = 6 ; Enable JTAG .equ OCDEN = 7 ; Enable OCD ; EXTENDED fuse bits .equ WDTON = 0 ; Watchdog timer always on .equ CompMode = 1 ; Compabillity mode ; * CPU REGISTER DEFINITIONS ************************************* .def XH = r27 .def XL = r26 .def YH = r29 .def YL = r28 .def ZH = r31 .def ZL = r30 ; * DATA MEMORY DECLARATIONS ************************************* .equ FLASHEND = 0x7fff ; Note: Word address .equ IOEND = 0x00ff .equ SRAM_START = 0x0100 .equ SRAM_SIZE = 4096 .equ RAMEND = 0x10ff .equ XRAMEND = 0xffff .equ E2END = 0x07ff .equ EEPROMEND = 0x07ff .equ EEADRBITS = 11 #pragma AVRPART MEMORY PROG_FLASH 65536 #pragma AVRPART MEMORY EEPROM 2048 #pragma AVRPART MEMORY INT_SRAM SIZE 4096 #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 ; * BOOTLOADER DECLARATIONS ************************************** .equ NRWW_START_ADDR = 0x7000 .equ NRWW_STOP_ADDR = 0x7fff .equ RWW_START_ADDR = 0x0 .equ RWW_STOP_ADDR = 0x6fff .equ PAGESIZE = 128 .equ FIRSTBOOTSTART = 0x7e00 .equ SECONDBOOTSTART = 0x7c00 .equ THIRDBOOTSTART = 0x7800 .equ FOURTHBOOTSTART = 0x7000 .equ SMALLBOOTSTART = FIRSTBOOTSTART .equ LARGEBOOTSTART = FOURTHBOOTSTART ; * INTERRUPT VECTORS ********************************************** .equ INT0addr = 0x0002 ; External Interrupt Request 0 .equ INT1addr = 0x0004 ; External Interrupt Request 1 .equ INT2addr = 0x0006 ; External Interrupt Request 2 .equ INT3addr = 0x0008 ; External Interrupt Request 3 .equ INT4addr = 0x000a ; External Interrupt Request 4 .equ INT5addr = 0x000c ; External Interrupt Request 5 .equ INT6addr = 0x000e ; External Interrupt Request 6 .equ INT7addr = 0x0010 ; External Interrupt Request 7 .equ OC2addr = 0x0012 ; Timer/Counter2 Compare Match .equ OVF2addr = 0x0014 ; Timer/Counter2 Overflow .equ ICP1addr = 0x0016 ; Timer/Counter1 Capture Event .equ OC1Aaddr = 0x0018 ; Timer/Counter1 Compare Match A .equ OC1Baddr = 0x001a ; Timer/Counter Compare Match B .equ OVF1addr = 0x001c ; Timer/Counter1 Overflow .equ OC0addr = 0x001e ; Timer/Counter0 Compare Match .equ OVF0addr = 0x0020 ; Timer/Counter0 Overflow .equ SPIaddr = 0x0022 ; SPI Serial Transfer Complete .equ URXC0addr = 0x0024 ; USART0, Rx Complete .equ UDRE0addr = 0x0026 ; USART0 Data Register Empty .equ UTXC0addr = 0x0028 ; USART0, Tx Complete .equ ADCCaddr = 0x002a ; ADC Conversion Complete .equ ERDYaddr = 0x002c ; EEPROM Ready .equ ACIaddr = 0x002e ; Analog Comparator .equ OC1Caddr = 0x0030 ; Timer/Counter1 Compare Match C .equ ICP3addr = 0x0032 ; Timer/Counter3 Capture Event .equ OC3Aaddr = 0x0034 ; Timer/Counter3 Compare Match A .equ OC3Baddr = 0x0036 ; Timer/Counter3 Compare Match B .equ OC3Caddr = 0x0038 ; Timer/Counter3 Compare Match C .equ OVF3addr = 0x003a ; Timer/Counter3 Overflow .equ URXC1addr = 0x003c ; USART1, Rx Complete .equ UDRE1addr = 0x003e ; USART1, Data Register Empty .equ UTXC1addr = 0x0040 ; USART1, Tx Complete .equ TWIaddr = 0x0042 ; 2-wire Serial Interface .equ SPMRaddr = 0x0044 ; Store Program Memory Read .equ INT_VECTORS_SIZE = 70 ; size in words #endif /* _M64DEF_INC_ / ; ** END OF FILE ****************************************************	/* Copyright (c) 2002, Steinar Haugen All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. / / $Id: iom64.h,v 1.14.2.5 2008/10/17 23:27:49 arcanum Exp $ / / avr/iom64.h - defines for ATmega64 As of 2002-11-23: - This should be up to date with data sheet Rev. 2490C-AVR-09/02 / #ifndef _AVR_IOM64_H_ #define _AVR_IOM64_H_ 1 / This file should only be included from <avr/io.h>, never directly. / #ifndef _AVR_IO_H_ # error "Include <avr/io.h> instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom64.h" #else # error "Attempt to include more than one <avr/ioXXX.h> file." #endif / I/O registers / / Input Pins, Port F / #define PINF _SFR_IO8(0x00) / Input Pins, Port E / #define PINE _SFR_IO8(0x01) / Data Direction Register, Port E / #define DDRE _SFR_IO8(0x02) / Data Register, Port E / #define PORTE _SFR_IO8(0x03) / ADC Data Register / #define ADCW _SFR_IO16(0x04) / for backwards compatibility / #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) / ADC Control and Status Register A / #define ADCSR _SFR_IO8(0x06) / for backwards compatibility / #define ADCSRA _SFR_IO8(0x06) / ADC Multiplexer select / #define ADMUX _SFR_IO8(0x07) / Analog Comparator Control and Status Register / #define ACSR _SFR_IO8(0x08) / USART0 Baud Rate Register Low / #define UBRR0L _SFR_IO8(0x09) / USART0 Control and Status Register B / #define UCSR0B _SFR_IO8(0x0A) / USART0 Control and Status Register A / #define UCSR0A _SFR_IO8(0x0B) / USART0 I/O Data Register / #define UDR0 _SFR_IO8(0x0C) / SPI Control Register / #define SPCR _SFR_IO8(0x0D) / SPI Status Register / #define SPSR _SFR_IO8(0x0E) / SPI I/O Data Register / #define SPDR _SFR_IO8(0x0F) / Input Pins, Port D / #define PIND _SFR_IO8(0x10) / Data Direction Register, Port D / #define DDRD _SFR_IO8(0x11) / Data Register, Port D / #define PORTD _SFR_IO8(0x12) / Input Pins, Port C / #define PINC _SFR_IO8(0x13) / Data Direction Register, Port C / #define DDRC _SFR_IO8(0x14) / Data Register, Port C / #define PORTC _SFR_IO8(0x15) / Input Pins, Port B / #define PINB _SFR_IO8(0x16) / Data Direction Register, Port B / #define DDRB _SFR_IO8(0x17) / Data Register, Port B / #define PORTB _SFR_IO8(0x18) / Input Pins, Port A / #define PINA _SFR_IO8(0x19) / Data Direction Register, Port A / #define DDRA _SFR_IO8(0x1A) / Data Register, Port A / #define PORTA _SFR_IO8(0x1B) / EEPROM Control Register / #define EECR _SFR_IO8(0x1C) / EEPROM Data Register / #define EEDR _SFR_IO8(0x1D) / EEPROM Address Register / #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEARH _SFR_IO8(0x1F) / Special Function I/O Register / #define SFIOR _SFR_IO8(0x20) / Watchdog Timer Control Register / #define WDTCR _SFR_IO8(0x21) / On-chip Debug Register / #define OCDR _SFR_IO8(0x22) / Timer2 Output Compare Register / #define OCR2 _SFR_IO8(0x23) / Timer/Counter 2 / #define TCNT2 _SFR_IO8(0x24) / Timer/Counter 2 Control register / #define TCCR2 _SFR_IO8(0x25) / T/C 1 Input Capture Register / #define ICR1 _SFR_IO16(0x26) #define ICR1L _SFR_IO8(0x26) #define ICR1H _SFR_IO8(0x27) / Timer/Counter1 Output Compare Register B / #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) / Timer/Counter1 Output Compare Register A / #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) / Timer/Counter 1 / #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) / Timer/Counter 1 Control and Status Register / #define TCCR1B _SFR_IO8(0x2E) / Timer/Counter 1 Control Register / #define TCCR1A _SFR_IO8(0x2F) / Timer/Counter 0 Asynchronous Control & Status Register / #define ASSR _SFR_IO8(0x30) / Output Compare Register 0 / #define OCR0 _SFR_IO8(0x31) / Timer/Counter 0 / #define TCNT0 _SFR_IO8(0x32) / Timer/Counter 0 Control Register / #define TCCR0 _SFR_IO8(0x33) / MCU Status Register / #define MCUSR _SFR_IO8(0x34) / for backwards compatibility / #define MCUCSR _SFR_IO8(0x34) / MCU general Control Register / #define MCUCR _SFR_IO8(0x35) / Timer/Counter Interrupt Flag Register / #define TIFR _SFR_IO8(0x36) / Timer/Counter Interrupt MaSK register / #define TIMSK _SFR_IO8(0x37) / External Interrupt Flag Register / #define EIFR _SFR_IO8(0x38) / External Interrupt MaSK register / #define EIMSK _SFR_IO8(0x39) / External Interrupt Control Register B / #define EICRB _SFR_IO8(0x3A) / XDIV Divide control register / #define XDIV _SFR_IO8(0x3C) / 0x3D..0x3E SP / / 0x3F SREG / / Extended I/O registers / / Data Direction Register, Port F / #define DDRF _SFR_MEM8(0x61) / Data Register, Port F / #define PORTF _SFR_MEM8(0x62) / Input Pins, Port G / #define PING _SFR_MEM8(0x63) / Data Direction Register, Port G / #define DDRG _SFR_MEM8(0x64) / Data Register, Port G / #define PORTG _SFR_MEM8(0x65) / Store Program Memory Control and Status Register / #define SPMCR _SFR_MEM8(0x68) #define SPMCSR _SFR_MEM8(0x68) / for backwards compatibility with m128/ / External Interrupt Control Register A / #define EICRA _SFR_MEM8(0x6A) / External Memory Control Register B / #define XMCRB _SFR_MEM8(0x6C) / External Memory Control Register A / #define XMCRA _SFR_MEM8(0x6D) / Oscillator Calibration Register / #define OSCCAL _SFR_MEM8(0x6F) / 2-wire Serial Interface Bit Rate Register / #define TWBR _SFR_MEM8(0x70) / 2-wire Serial Interface Status Register / #define TWSR _SFR_MEM8(0x71) / 2-wire Serial Interface Address Register / #define TWAR _SFR_MEM8(0x72) / 2-wire Serial Interface Data Register / #define TWDR _SFR_MEM8(0x73) / 2-wire Serial Interface Control Register / #define TWCR _SFR_MEM8(0x74) / Time Counter 1 Output Compare Register C / #define OCR1C _SFR_MEM16(0x78) #define OCR1CL _SFR_MEM8(0x78) #define OCR1CH _SFR_MEM8(0x79) / Timer/Counter 1 Control Register C / #define TCCR1C _SFR_MEM8(0x7A) / Extended Timer Interrupt Flag Register / #define ETIFR _SFR_MEM8(0x7C) / Extended Timer Interrupt Mask Register / #define ETIMSK _SFR_MEM8(0x7D) / Timer/Counter 3 Input Capture Register / #define ICR3 _SFR_MEM16(0x80) #define ICR3L _SFR_MEM8(0x80) #define ICR3H _SFR_MEM8(0x81) / Timer/Counter 3 Output Compare Register C / #define OCR3C _SFR_MEM16(0x82) #define OCR3CL _SFR_MEM8(0x82) #define OCR3CH _SFR_MEM8(0x83) / Timer/Counter 3 Output Compare Register B / #define OCR3B _SFR_MEM16(0x84) #define OCR3BL _SFR_MEM8(0x84) #define OCR3BH _SFR_MEM8(0x85) / Timer/Counter 3 Output Compare Register A / #define OCR3A _SFR_MEM16(0x86) #define OCR3AL _SFR_MEM8(0x86) #define OCR3AH _SFR_MEM8(0x87) / Timer/Counter 3 Counter Register / #define TCNT3 _SFR_MEM16(0x88) #define TCNT3L _SFR_MEM8(0x88) #define TCNT3H _SFR_MEM8(0x89) / Timer/Counter 3 Control Register B / #define TCCR3B _SFR_MEM8(0x8A) / Timer/Counter 3 Control Register A / #define TCCR3A _SFR_MEM8(0x8B) / Timer/Counter 3 Control Register C / #define TCCR3C _SFR_MEM8(0x8C) / ADC Control and Status Register B / #define ADCSRB _SFR_MEM8(0x8E) / USART0 Baud Rate Register High / #define UBRR0H _SFR_MEM8(0x90) / USART0 Control and Status Register C / #define UCSR0C _SFR_MEM8(0x95) / USART1 Baud Rate Register High / #define UBRR1H _SFR_MEM8(0x98) / USART1 Baud Rate Register Low/ #define UBRR1L _SFR_MEM8(0x99) / USART1 Control and Status Register B / #define UCSR1B _SFR_MEM8(0x9A) / USART1 Control and Status Register A / #define UCSR1A _SFR_MEM8(0x9B) / USART1 I/O Data Register / #define UDR1 _SFR_MEM8(0x9C) / USART1 Control and Status Register C / #define UCSR1C _SFR_MEM8(0x9D) / Interrupt vectors / / External Interrupt Request 0 / #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) / External Interrupt Request 1 / #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) / External Interrupt Request 2 / #define INT2_vect _VECTOR(3) #define SIG_INTERRUPT2 _VECTOR(3) / External Interrupt Request 3 / #define INT3_vect _VECTOR(4) #define SIG_INTERRUPT3 _VECTOR(4) / External Interrupt Request 4 / #define INT4_vect _VECTOR(5) #define SIG_INTERRUPT4 _VECTOR(5) / External Interrupt Request 5 / #define INT5_vect _VECTOR(6) #define SIG_INTERRUPT5 _VECTOR(6) / External Interrupt Request 6 / #define INT6_vect _VECTOR(7) #define SIG_INTERRUPT6 _VECTOR(7) / External Interrupt Request 7 / #define INT7_vect _VECTOR(8) #define SIG_INTERRUPT7 _VECTOR(8) / Timer/Counter2 Compare Match / #define TIMER2_COMP_vect _VECTOR(9) #define SIG_OUTPUT_COMPARE2 _VECTOR(9) / Timer/Counter2 Overflow / #define TIMER2_OVF_vect _VECTOR(10) #define SIG_OVERFLOW2 _VECTOR(10) / Timer/Counter1 Capture Event / #define TIMER1_CAPT_vect _VECTOR(11) #define SIG_INPUT_CAPTURE1 _VECTOR(11) / Timer/Counter1 Compare Match A / #define TIMER1_COMPA_vect _VECTOR(12) #define SIG_OUTPUT_COMPARE1A _VECTOR(12) / Timer/Counter Compare Match B / #define TIMER1_COMPB_vect _VECTOR(13) #define SIG_OUTPUT_COMPARE1B _VECTOR(13) / Timer/Counter1 Overflow / #define TIMER1_OVF_vect _VECTOR(14) #define SIG_OVERFLOW1 _VECTOR(14) / Timer/Counter0 Compare Match / #define TIMER0_COMP_vect _VECTOR(15) #define SIG_OUTPUT_COMPARE0 _VECTOR(15) / Timer/Counter0 Overflow / #define TIMER0_OVF_vect _VECTOR(16) #define SIG_OVERFLOW0 _VECTOR(16) / SPI Serial Transfer Complete / #define SPI_STC_vect _VECTOR(17) #define SIG_SPI _VECTOR(17) / USART0, Rx Complete / #define USART0_RX_vect _VECTOR(18) #define SIG_UART0_RECV _VECTOR(18) / USART0 Data Register Empty / #define USART0_UDRE_vect _VECTOR(19) #define SIG_UART0_DATA _VECTOR(19) / USART0, Tx Complete / #define USART0_TX_vect _VECTOR(20) #define SIG_UART0_TRANS _VECTOR(20) / ADC Conversion Complete / #define ADC_vect _VECTOR(21) #define SIG_ADC _VECTOR(21) / EEPROM Ready / #define EE_READY_vect _VECTOR(22) #define SIG_EEPROM_READY _VECTOR(22) / Analog Comparator / #define ANALOG_COMP_vect _VECTOR(23) #define SIG_COMPARATOR _VECTOR(23) / Timer/Counter1 Compare Match C / #define TIMER1_COMPC_vect _VECTOR(24) #define SIG_OUTPUT_COMPARE1C _VECTOR(24) / Timer/Counter3 Capture Event / #define TIMER3_CAPT_vect _VECTOR(25) #define SIG_INPUT_CAPTURE3 _VECTOR(25) / Timer/Counter3 Compare Match A / #define TIMER3_COMPA_vect _VECTOR(26) #define SIG_OUTPUT_COMPARE3A _VECTOR(26) / Timer/Counter3 Compare Match B / #define TIMER3_COMPB_vect _VECTOR(27) #define SIG_OUTPUT_COMPARE3B _VECTOR(27) / Timer/Counter3 Compare Match C / #define TIMER3_COMPC_vect _VECTOR(28) #define SIG_OUTPUT_COMPARE3C _VECTOR(28) / Timer/Counter3 Overflow / #define TIMER3_OVF_vect _VECTOR(29) #define SIG_OVERFLOW3 _VECTOR(29) / USART1, Rx Complete / #define USART1_RX_vect _VECTOR(30) #define SIG_UART1_RECV _VECTOR(30) / USART1, Data Register Empty / #define USART1_UDRE_vect _VECTOR(31) #define SIG_UART1_DATA _VECTOR(31) / USART1, Tx Complete / #define USART1_TX_vect _VECTOR(32) #define SIG_UART1_TRANS _VECTOR(32) / 2-wire Serial Interface / #define TWI_vect _VECTOR(33) #define SIG_2WIRE_SERIAL _VECTOR(33) / Store Program Memory Read / #define SPM_READY_vect _VECTOR(34) #define SIG_SPM_READY _VECTOR(34) #define _VECTORS_SIZE 140 / The Register Bit names are represented by their bit number (0-7). / / 2-wire Control Register - TWCR / #define TWINT 7 #define TWEA 6 #define TWSTA 5 #define TWSTO 4 #define TWWC 3 #define TWEN 2 #define TWIE 0 / 2-wire Address Register - TWAR / #define TWA6 7 #define TWA5 6 #define TWA4 5 #define TWA3 4 #define TWA2 3 #define TWA1 2 #define TWA0 1 #define TWGCE 0 / 2-wire Status Register - TWSR / #define TWS7 7 #define TWS6 6 #define TWS5 5 #define TWS4 4 #define TWS3 3 #define TWPS1 1 #define TWPS0 0 / External Memory Control Register A - XMCRA / #define SRL2 6 #define SRL1 5 #define SRL0 4 #define SRW01 3 #define SRW00 2 #define SRW11 1 / External Memory Control Register B - XMCRA / #define XMBK 7 #define XMM2 2 #define XMM1 1 #define XMM0 0 / XDIV Divide control register - XDIV / #define XDIVEN 7 #define XDIV6 6 #define XDIV5 5 #define XDIV4 4 #define XDIV3 3 #define XDIV2 2 #define XDIV1 1 #define XDIV0 0 / External Interrupt Control Register A - EICRA / #define ISC31 7 #define ISC30 6 #define ISC21 5 #define ISC20 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 / External Interrupt Control Register B - EICRB / #define ISC71 7 #define ISC70 6 #define ISC61 5 #define ISC60 4 #define ISC51 3 #define ISC50 2 #define ISC41 1 #define ISC40 0 / Store Program Memory Control Register - SPMCSR, SPMCR / #define SPMIE 7 #define RWWSB 6 #define RWWSRE 4 #define BLBSET 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 / External Interrupt MaSK register - EIMSK / #define INT7 7 #define INT6 6 #define INT5 5 #define INT4 4 #define INT3 3 #define INT2 2 #define INT1 1 #define INT0 0 / External Interrupt Flag Register - EIFR / #define INTF7 7 #define INTF6 6 #define INTF5 5 #define INTF4 4 #define INTF3 3 #define INTF2 2 #define INTF1 1 #define INTF0 0 / Timer/Counter Interrupt MaSK register - TIMSK / #define OCIE2 7 #define TOIE2 6 #define TICIE1 5 #define OCIE1A 4 #define OCIE1B 3 #define TOIE1 2 #define OCIE0 1 #define TOIE0 0 / Timer/Counter Interrupt Flag Register - TIFR / #define OCF2 7 #define TOV2 6 #define ICF1 5 #define OCF1A 4 #define OCF1B 3 #define TOV1 2 #define OCF0 1 #define TOV0 0 / Extended Timer Interrupt MaSK register - ETIMSK / #define TICIE3 5 #define OCIE3A 4 #define OCIE3B 3 #define TOIE3 2 #define OCIE3C 1 #define OCIE1C 0 / Extended Timer Interrupt Flag Register - ETIFR / #define ICF3 5 #define OCF3A 4 #define OCF3B 3 #define TOV3 2 #define OCF3C 1 #define OCF1C 0 / MCU Control Register - MCUCR / #define SRE 7 #define SRW10 6 #define SE 5 #define SM1 4 #define SM0 3 #define SM2 2 #define IVSEL 1 #define IVCE 0 / MCU Control And Status Register - MCUCSR / #define JTD 7 #define JTRF 4 #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 / Timer/Counter Control Register (generic) / #define FOC 7 #define WGM0 6 #define COM1 5 #define COM0 4 #define WGM1 3 #define CS2 2 #define CS1 1 #define CS0 0 / Timer/Counter 0 Control Register - TCCR0 / #define FOC0 7 #define WGM00 6 #define COM01 5 #define COM00 4 #define WGM01 3 #define CS02 2 #define CS01 1 #define CS00 0 / Timer/Counter 2 Control Register - TCCR2 / #define FOC2 7 #define WGM20 6 #define COM21 5 #define COM20 4 #define WGM21 3 #define CS22 2 #define CS21 1 #define CS20 0 / Timer/Counter 0 Asynchronous Control & Status Register - ASSR / #define AS0 3 #define TCN0UB 2 #define OCR0UB 1 #define TCR0UB 0 / Timer/Counter Control Register A (generic) / #define COMA1 7 #define COMA0 6 #define COMB1 5 #define COMB0 4 #define COMC1 3 #define COMC0 2 #define WGMA1 1 #define WGMA0 0 / Timer/Counter 1 Control and Status Register A - TCCR1A / #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define COM1C1 3 #define COM1C0 2 #define WGM11 1 #define WGM10 0 / Timer/Counter 3 Control and Status Register A - TCCR3A / #define COM3A1 7 #define COM3A0 6 #define COM3B1 5 #define COM3B0 4 #define COM3C1 3 #define COM3C0 2 #define WGM31 1 #define WGM30 0 / Timer/Counter Control and Status Register B (generic) / #define ICNC 7 #define ICES 6 #define WGMB3 4 #define WGMB2 3 #define CSB2 2 #define CSB1 1 #define CSB0 0 / Timer/Counter 1 Control and Status Register B - TCCR1B / #define ICNC1 7 #define ICES1 6 #define WGM13 4 #define WGM12 3 #define CS12 2 #define CS11 1 #define CS10 0 / Timer/Counter 3 Control and Status Register B - TCCR3B / #define ICNC3 7 #define ICES3 6 #define WGM33 4 #define WGM32 3 #define CS32 2 #define CS31 1 #define CS30 0 / Timer/Counter Control Register C (generic) / #define FOCA 7 #define FOCB 6 #define FOCC 5 / Timer/Counter 3 Control Register C - TCCR3C / #define FOC3A 7 #define FOC3B 6 #define FOC3C 5 / Timer/Counter 1 Control Register C - TCCR1C / #define FOC1A 7 #define FOC1B 6 #define FOC1C 5 / On-chip Debug Register - OCDR / #define IDRD 7 #define OCDR7 7 #define OCDR6 6 #define OCDR5 5 #define OCDR4 4 #define OCDR3 3 #define OCDR2 2 #define OCDR1 1 #define OCDR0 0 / Watchdog Timer Control Register - WDTCR / #define WDCE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 / The ADHSM bit has been removed from all documentation, as being not needed at all since the comparator has proven to be fast enough even without feeding it more power. / / Special Function I/O Register - SFIOR / #define TSM 7 #define ACME 3 #define PUD 2 #define PSR0 1 #define PSR321 0 / Port Data Register (generic) / #define PORT7 7 #define PORT6 6 #define PORT5 5 #define PORT4 4 #define PORT3 3 #define PORT2 2 #define PORT1 1 #define PORT0 0 / Port Data Direction Register (generic) / #define DD7 7 #define DD6 6 #define DD5 5 #define DD4 4 #define DD3 3 #define DD2 2 #define DD1 1 #define DD0 0 / Port Input Pins (generic) / #define PIN7 7 #define PIN6 6 #define PIN5 5 #define PIN4 4 #define PIN3 3 #define PIN2 2 #define PIN1 1 #define PIN0 0 / SPI Status Register - SPSR / #define SPIF 7 #define WCOL 6 #define SPI2X 0 / SPI Control Register - SPCR / #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 / USART Register C (generic) / #define UMSEL 6 #define UPM1 5 #define UPM0 4 #define USBS 3 #define UCSZ1 2 #define UCSZ0 1 #define UCPOL 0 / USART1 Register C - UCSR1C / #define UMSEL1 6 #define UPM11 5 #define UPM10 4 #define USBS1 3 #define UCSZ11 2 #define UCSZ10 1 #define UCPOL1 0 / USART0 Register C - UCSR0C / #define UMSEL0 6 #define UPM01 5 #define UPM00 4 #define USBS0 3 #define UCSZ01 2 #define UCSZ00 1 #define UCPOL0 0 / USART Status Register A (generic) / #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 #define UPE 2 #define U2X 1 #define MPCM 0 / USART1 Status Register A - UCSR1A / #define RXC1 7 #define TXC1 6 #define UDRE1 5 #define FE1 4 #define DOR1 3 #define UPE1 2 #define U2X1 1 #define MPCM1 0 / USART0 Status Register A - UCSR0A / #define RXC0 7 #define TXC0 6 #define UDRE0 5 #define FE0 4 #define DOR0 3 #define UPE0 2 #define U2X0 1 #define MPCM0 0 / USART Control Register B (generic) / #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define UCSZ 2 #define UCSZ2 2 / new name in datasheet (2467E-AVR-05/02) / #define RXB8 1 #define TXB8 0 / USART1 Control Register B - UCSR1B / #define RXCIE1 7 #define TXCIE1 6 #define UDRIE1 5 #define RXEN1 4 #define TXEN1 3 #define UCSZ12 2 #define RXB81 1 #define TXB81 0 / USART0 Control Register B - UCSR0B / #define RXCIE0 7 #define TXCIE0 6 #define UDRIE0 5 #define RXEN0 4 #define TXEN0 3 #define UCSZ02 2 #define RXB80 1 #define TXB80 0 / Analog Comparator Control and Status Register - ACSR / #define ACD 7 #define ACBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 / ADC Control and Status Register B - ADCSRB / #define ADTS2 2 #define ADTS1 1 #define ADTS0 0 / ADC Control and status Register A - ADCSRA / #define ADEN 7 #define ADSC 6 #define ADATE 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 / ADC Multiplexer select - ADMUX / #define REFS1 7 #define REFS0 6 #define ADLAR 5 #define MUX4 4 #define MUX3 3 #define MUX2 2 #define MUX1 1 #define MUX0 0 / Port A Data Register - PORTA / #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 / Port A Data Direction Register - DDRA / #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 / Port A Input Pins - PINA / #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 / Port B Data Register - PORTB / #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 / Port B Data Direction Register - DDRB / #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 / Port B Input Pins - PINB / #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 / Port C Data Register - PORTC / #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 / Port C Data Direction Register - DDRC / #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 / Port C Input Pins - PINC / #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 / Port D Data Register - PORTD / #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 / Port D Data Direction Register - DDRD / #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 / Port D Input Pins - PIND / #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 / Port E Data Register - PORTE / #define PE7 7 #define PE6 6 #define PE5 5 #define PE4 4 #define PE3 3 #define PE2 2 #define PE1 1 #define PE0 0 / Port E Data Direction Register - DDRE / #define DDE7 7 #define DDE6 6 #define DDE5 5 #define DDE4 4 #define DDE3 3 #define DDE2 2 #define DDE1 1 #define DDE0 0 / Port E Input Pins - PINE / #define PINE7 7 #define PINE6 6 #define PINE5 5 #define PINE4 4 #define PINE3 3 #define PINE2 2 #define PINE1 1 #define PINE0 0 / Port F Data Register - PORTF / #define PF7 7 #define PF6 6 #define PF5 5 #define PF4 4 #define PF3 3 #define PF2 2 #define PF1 1 #define PF0 0 / Port F Data Direction Register - DDRF / #define DDF7 7 #define DDF6 6 #define DDF5 5 #define DDF4 4 #define DDF3 3 #define DDF2 2 #define DDF1 1 #define DDF0 0 / Port F Input Pins - PINF / #define PINF7 7 #define PINF6 6 #define PINF5 5 #define PINF4 4 #define PINF3 3 #define PINF2 2 #define PINF1 1 #define PINF0 0 / Port G Data Register - PORTG / #define PG4 4 #define PG3 3 #define PG2 2 #define PG1 1 #define PG0 0 / Port G Data Direction Register - DDRG / #define DDG4 4 #define DDG3 3 #define DDG2 2 #define DDG1 1 #define DDG0 0 / Port G Input Pins - PING / #define PING4 4 #define PING3 3 #define PING2 2 #define PING1 1 #define PING0 0 / EEPROM Control Register / #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 / Constants / #define SPM_PAGESIZE 256 #define RAMEND 0x10FF / Last On-Chip SRAM Location / #define XRAMEND 0xFFFF #define E2END 0x07FF #define E2PAGESIZE 8 #define FLASHEND 0xFFFF / Fuses / #define FUSE_MEMORY_SIZE 3 / Low Fuse Byte / #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_BODEN (unsigned char)~_BV(6) #define FUSE_BODLEVEL (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) / High Fuse Byte / #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_CKOPT (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) / Extended Fuse Byte / #define FUSE_WDTON (unsigned char)~_BV(0) #define FUSE_M103C (unsigned char)~_BV(1) #define EFUSE_DEFAULT (FUSE_M103C) / Lock Bits / #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST / Signature / #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x96 #define SIGNATURE_2 0x02 #endif / _AVR_IOM64_H_ */

ATtiny2313

ATmega8

ATmega16

ATmega32

ATmega48

ATmega64

ATtiny2313

ATmega8

ATmega16

ATmega32

ATmega48

ATmega64