:ISP: Schieberegister

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DECLARATIONS
  takt       PIN 11;                                   "Takt vom Taktgenerator
  serDaten   PIN 16;                                   "serieller Dateneingang
  bit7..bit0 PIN 3,4,5,6,7,8,9,10 ISTYPE 'BUFFER,REG'; "SRG-FFs an LEDs 

EQUATIONS
  bit0.d = serDaten;  "Daten schieben
  bit1.d = bit0.q;
  bit2.d = bit1.q;
  bit3.d = bit2.q;
  bit4.d = bit3.q;
  bit5.d = bit4.q;
  bit6.d = bit5.q;
  bit7.d = bit6.q;

  bit0.clk = takt;   "synchrones SRG
  bit1.clk = takt;
  bit2.clk = takt;
  bit3.clk = takt;
  bit4.clk = takt;
  bit5.clk = takt;
  bit6.clk = takt;
  bit7.clk = takt;

TEST_VECTORS
            ([takt,serDaten] -> [bit0..bit7]);
             [.c. , 1      ] -> .x.;
             [.c. , 0      ] -> .x.;
             [.c. , 1      ] -> .x.;
  @repeat 8 {[.c. , 0      ] -> .x.;}

END

  Simulation:

MODULE SRG8ps
  "Schieberegister mit 8 Bit parallel seriell

DECLARATIONS
  takt       PIN 11;                                   "Takt vom Taktgenerator
  laden      PIN 16;                                   "Laden wenn T1 gedrückt
  d7..d0     PIN 25,26,27,28,29,30,31,32;              "parallele Dateneingänge
  bit7..bit0 PIN 3,4,5,6,7,8,9,10 ISTYPE 'BUFFER,REG'; "SRG-FFs an LEDs

  srg   = [bit7..bit0];
  daten = [d7..d0];

EQUATIONS
  when laden then srg.d = daten
             else { bit7.d =   1;
                    bit6.d =   bit7.q;
                    bit5.d =   bit6.q;
                    bit4.d =   bit5.q;
                    bit3.d =   bit4.q;
                    bit2.d =   bit3.q;
                    bit1.d =   bit2.q;
                    bit0.d =   bit1.q;
                   }
  srg.clk = takt;
  
TEST_VECTORS
            ([takt,laden,d7..d0         ] -> [bit0..bit7]);
             [.c. , 1   ,1,1,0,1,1,1,0,1] -> .x.;
 @repeat 8  {[.c. , 0   ,1,1,0,1,1,1,0,1] -> .x.;}

END